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    Memory management based on classification of a software process
    1.
    发明授权
    Memory management based on classification of a software process 有权

    公开(公告)号：US11301296B2

    公开(公告)日：2022-04-12

    申请号：US16808021

    申请日：2020-03-03

    Applicant: Apple Inc.

    Inventor： Kushal Dalmia ,  Andrey V. Talnikov ,  Lionel D. Desai ,  Russell A. Blaine

    IPC: G06F9/46 ,  G06F9/50 ,  G06F11/34 ,  G06F11/30

    Abstract: Memory management in a data processing system can learn one or more behaviors of software processes such as daemon software processes and application processes, and based on information learned about the behaviors, the memory management can adjust how it controls memory usage in the system. For example, a memory management system can learn how software processes react (e.g. how quickly they relaunch) to memory recovery methods, such as system initiated terminations of one or more software processes that are performed to reclaim memory to increase available volatile memory, and based on information about how they react, the memory recovery methods can operate differently depending upon how the software reacted previously.

    MEMORY MANAGEMENT IN DATA PROCESSING SYSTEMS
    2.
    发明申请
    MEMORY MANAGEMENT IN DATA PROCESSING SYSTEMS 有权

    公开(公告)号：US20220222116A1

    公开(公告)日：2022-07-14

    申请号：US17699911

    申请日：2022-03-21

    Applicant: Apple Inc.

    Inventor： Kushal Dalmia ,  Andrey V. Talnikov ,  Lionel D. Desai ,  Russell A. Blaine

    IPC: G06F9/50 ,  G06F11/34 ,  G06F11/30

    Abstract: Memory management in a data processing system can learn one or more behaviors of software processes such as daemon software processes and application processes, and based on information learned about the behaviors, the memory management can adjust how it controls memory usage in the system. For example, a memory management system can learn how software processes react (e.g. how quickly they relaunch) to memory recovery methods, such as system initiated terminations of one or more software processes that are performed to reclaim memory to increase available volatile memory, and based on information about how they react, the memory recovery methods can operate differently depending upon how the software reacted previously.

    CPU cluster shared resource management
    3.
    发明授权
    CPU cluster shared resource management 有权

    公开(公告)号：US12147839B2

    公开(公告)日：2024-11-19

    申请号：US17392929

    申请日：2021-08-03

    Applicant: Apple Inc.

    Inventor： John G. Dorsey ,  Bryan R. Hinch ,  Ronit Banerjee ,  Kushal Dalmia ,  Daniel A. Chimene ,  Jaidev P. Patwardhan

    IPC: G06F9/50 ,  G06F9/48 ,  G06F11/14

    Abstract: Embodiments include an asymmetric multiprocessing (AMP) system having a first central processing unit (CPU) cluster comprising a first core type, and a second CPU cluster comprising a second core type, where the AMP system can update a thread metric for a first thread running on the first CPU cluster based at least on: a past shared resource overloaded metric of the first CPU cluster, and on-core metrics of the first thread. The on-core metrics can indicate that first thread contributes to contention of the same shared resource corresponding to the past shared resource overloaded metric of the first CPU cluster. The AMP system can assign the first thread to a different CPU cluster while other threads of the same thread group remain assigned to the first CPU cluster. The thread metric can include a Matrix Extension (MX) thread flag or a Bus Interface Unit (BIU) thread flag.

    Multi-level scheduling
    5.
    发明授权
    Multi-level scheduling 有权

    公开(公告)号：US11422857B2

    公开(公告)日：2022-08-23

    申请号：US16882092

    申请日：2020-05-22

    Applicant: Apple Inc.

    Inventor： Kushal Dalmia ,  Jeremy C. Andrus ,  Daniel A. Chimene ,  Nigel R. Gamble ,  James M. Magee ,  Daniel A. Steffen

    IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50

    Abstract: Embodiments described herein provide multi-level scheduling for threads in a data processing system. One embodiment provides a data processing system comprising one or more processors, a computer-readable memory coupled to the one or more processors, the computer-readable memory to store instructions which, when executed by the one or more processors, configure the one or more processors to receive execution threads for execution on the one or more processors, map the execution threads into a first plurality of buckets based at least in part on a quality of service class of the execution threads, schedule the first plurality of buckets for execution using a first scheduling algorithm, schedule a second plurality thread groups within the first plurality of buckets for execution using a second scheduling algorithm, and schedule a third plurality of threads within the second plurality of thread groups using a third scheduling algorithm.

    MEMORY MANAGEMENT IN DATA PROCESSING SYSTEMS
    6.
    发明申请
    MEMORY MANAGEMENT IN DATA PROCESSING SYSTEMS 审中-公开

    公开(公告)号：US20200379810A1

    公开(公告)日：2020-12-03

    申请号：US16808021

    申请日：2020-03-03

    Applicant: Apple Inc.

    Inventor： Kushal Dalmia ,  Andrey V. Talnikov ,  Lionel D. Desai ,  Russell A. Blaine

    IPC: G06F9/50 ,  G06F11/30 ,  G06F11/34

    Abstract: Memory management in a data processing system can learn one or more behaviors of software processes such as daemon software processes and application processes, and based on information learned about the behaviors, the memory management can adjust how it controls memory usage in the system. For example, a memory management system can learn how software processes react (e.g. how quickly they relaunch) to memory recovery methods, such as system initiated terminations of one or more software processes that are performed to reclaim memory to increase available volatile memory, and based on information about how they react, the memory recovery methods can operate differently depending upon how the software reacted previously.

    SCHEDULER FOR AMP ARCHITECTURE USING A CLOSED LOOP PERFORMANCE CONTROLLER AND DEFERRED INTER-PROCESSOR INTERRUPTS
    7.
    发明申请
    SCHEDULER FOR AMP ARCHITECTURE USING A CLOSED LOOP PERFORMANCE CONTROLLER AND DEFERRED INTER-PROCESSOR INTERRUPTS 审中-公开

    公开(公告)号：US20180349177A1

    公开(公告)日：2018-12-06

    申请号：US15870770

    申请日：2018-01-12

    Applicant: Apple Inc.

    Inventor： Constantin Pistol ,  Daniel A. Chimene ,  Jeremy C. Andrus ,  Russell A. Blaine ,  Kushal Dalmia

    IPC: G06F9/48 ,  G06F9/38 ,  G06F9/26 ,  G06F9/50 ,  G06F9/30

    Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

    MULTI-LEVEL SCHEDULING
    10.
    发明申请
    MULTI-LEVEL SCHEDULING 审中-公开

    公开(公告)号：US20200379804A1

    公开(公告)日：2020-12-03

    申请号：US16882092

    申请日：2020-05-22

    Applicant: Apple Inc.

    Inventor： Kushal Dalmia ,  Jeremy C. Andrus ,  Daniel A. Chimene ,  Nigel R. Gamble ,  James M. Magee ,  Daniel A. Steffen

    IPC: G06F9/48 ,  G06F9/50

    Abstract: Embodiments described herein provide multi-level scheduling for threads in a data processing system. One embodiment provides a data processing system comprising one or more processors, a computer-readable memory coupled to the one or more processors, the computer-readable memory to store instructions which, when executed by the one or more processors, configure the one or more processors to receive execution threads for execution on the one or more processors, map the execution threads into a first plurality of buckets based at least in part on a quality of service class of the execution threads, schedule the first plurality of buckets for execution using a first scheduling algorithm, schedule a second plurality thread groups within the first plurality of buckets for execution using a second scheduling algorithm, and schedule a third plurality of threads within the second plurality of thread groups using a third scheduling algorithm.

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