公开(公告)号：US20230385201A1

公开(公告)日：2023-11-30

申请号：US18362686

申请日：2023-07-31

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Terence M. Potter ,  Anjana Rajendran ,  Mark I. Luffel ,  William V. Miller

IPC: G06F12/1009 ,  G06F9/38 ,  G06T1/60 ,  G06T1/20

CPC classification number: G06F12/1009 ,  G06F9/3887 ,  G06T1/60 ,  G06T1/20 ,  G06F2212/657

Abstract: Techniques are disclosed relating to private memory management using a mapping thread, which may be persistent. In some embodiments, a graphics processor is configured to generate a pool of private memory pages for a set of graphics work that includes multiple threads. The processor may maintain a translation table configured to map private memory addresses to virtual addresses based on identifiers of the threads. The processor may execute a mapping thread to receive a request to allocate a private memory page for a requesting thread, select a private memory page from the pool in response to the request, and map the selected page in the translation table for the requesting. The processor may then execute one or more instructions of the requesting thread to access a private memory space, wherein the execution includes translation of a private memory address to a virtual address based on the mapped page in the translation table. The mapping thread may be a persistent thread for which resources are allocated for an entirety of a time interval over which the set of graphics work is executed.

公开(公告)号：US11714759B2

公开(公告)日：2023-08-01

申请号：US16995450

申请日：2020-08-17

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Terence M. Potter ,  Anjana Rajendran ,  Mark I. Luffel ,  William V. Miller

IPC: G06F12/00 ,  G06F12/1009 ,  G06F9/38 ,  G06T1/60 ,  G06T1/20

CPC classification number: G06F12/1009 ,  G06F9/3887 ,  G06T1/20 ,  G06T1/60 ,  G06F2212/657

Abstract: Techniques are disclosed relating to private memory management using a mapping thread, which may be persistent. In some embodiments, a graphics processor is configured to generate a pool of private memory pages for a set of graphics work that includes multiple threads. The processor may maintain a translation table configured to map private memory addresses to virtual addresses based on identifiers of the threads. The processor may execute a mapping thread to receive a request to allocate a private memory page for a requesting thread, select a private memory page from the pool in response to the request, and map the selected page in the translation table for the requesting. The processor may then execute one or more instructions of the requesting thread to access a private memory space, wherein the execution includes translation of a private memory address to a virtual address based on the mapped page in the translation table. The mapping thread may be a persistent thread for which resources are allocated for an entirety of a time interval over which the set of graphics work is executed.