公开(公告)号：US20240095065A1

公开(公告)日：2024-03-21

申请号：US18054376

申请日：2022-11-10

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Anjana Rajendran ,  Sheenam Jayaswal ,  Terence M. Potter ,  Yoong Chert Foo

IPC: G06F9/48

CPC classification number: G06F9/4881 ,  G06F9/485

Abstract: Techniques are disclosed relating to multi-stage thread scheduling. In some embodiments, processor circuitry includes multiple channel pipelines for multiple channels and multiple execution pipelines shared by the channel pipelines and configured to perform different types of operations provided by the channel pipelines. First scheduler circuitry may arbitrate among threads to assign threads to channels. Second scheduler circuitry may arbitrate among channels to assign an operation from a given channel to a given execution pipeline. The execution pipelines may provide backpressure information to the first scheduler circuitry based on execution status and the first scheduler circuitry may adjust priority of a thread for assignment to a channel based on the backpressure information. Disclosed techniques may reduce channel conflicts and starvation for execution resources.

公开(公告)号：US20230385201A1

公开(公告)日：2023-11-30

申请号：US18362686

申请日：2023-07-31

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Terence M. Potter ,  Anjana Rajendran ,  Mark I. Luffel ,  William V. Miller

IPC: G06F12/1009 ,  G06F9/38 ,  G06T1/60 ,  G06T1/20

CPC classification number: G06F12/1009 ,  G06F9/3887 ,  G06T1/60 ,  G06T1/20 ,  G06F2212/657

Abstract: Techniques are disclosed relating to private memory management using a mapping thread, which may be persistent. In some embodiments, a graphics processor is configured to generate a pool of private memory pages for a set of graphics work that includes multiple threads. The processor may maintain a translation table configured to map private memory addresses to virtual addresses based on identifiers of the threads. The processor may execute a mapping thread to receive a request to allocate a private memory page for a requesting thread, select a private memory page from the pool in response to the request, and map the selected page in the translation table for the requesting. The processor may then execute one or more instructions of the requesting thread to access a private memory space, wherein the execution includes translation of a private memory address to a virtual address based on the mapped page in the translation table. The mapping thread may be a persistent thread for which resources are allocated for an entirety of a time interval over which the set of graphics work is executed.

公开(公告)号：US12190151B2

公开(公告)日：2025-01-07

申请号：US18054376

申请日：2022-11-10

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Anjana Rajendran ,  Sheenam Jayaswal ,  Terence M. Potter ,  Yoong Chert Foo

IPC: G06F9/48

Abstract: Techniques are disclosed relating to multi-stage thread scheduling. In some embodiments, processor circuitry includes multiple channel pipelines for multiple channels and multiple execution pipelines shared by the channel pipelines and configured to perform different types of operations provided by the channel pipelines. First scheduler circuitry may arbitrate among threads to assign threads to channels. Second scheduler circuitry may arbitrate among channels to assign an operation from a given channel to a given execution pipeline. The execution pipelines may provide backpressure information to the first scheduler circuitry based on execution status and the first scheduler circuitry may adjust priority of a thread for assignment to a channel based on the backpressure information. Disclosed techniques may reduce channel conflicts and starvation for execution resources.

公开(公告)号：US11204774B1

公开(公告)日：2021-12-21

申请号：US17008518

申请日：2020-08-31

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Anjana Rajendran ,  Jeffrey A. Lohman ,  Terence M. Potter

IPC: G06F9/38

Abstract: Techniques are disclosed relating to a thread-group-scoped gate instruction. In some embodiments, graphics processor circuitry is configured to execute, for multiple SIMD groups of a thread group, a graphics program that includes a gate instruction. During execution of the gate instruction for a first SIMD group, the processor accesses state information to determine that a threshold number of other SIMD groups in the thread group have not yet executed the gate instruction. Based on the determination, the processor executes a particular set of instructions of the graphics program for the first SIMD group (that is not executed by one or more other SIMD groups that reach the gate instruction after the first SIMD group). For example, the particular set of instructions may be a utility program that performs one or more operations for the entire thread group but is only executed by a subset of the SIMD groups.

公开(公告)号：US11714759B2

公开(公告)日：2023-08-01

申请号：US16995450

申请日：2020-08-17

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Terence M. Potter ,  Anjana Rajendran ,  Mark I. Luffel ,  William V. Miller

IPC: G06F12/00 ,  G06F12/1009 ,  G06F9/38 ,  G06T1/60 ,  G06T1/20

CPC classification number: G06F12/1009 ,  G06F9/3887 ,  G06T1/20 ,  G06T1/60 ,  G06F2212/657

Abstract: Techniques are disclosed relating to private memory management using a mapping thread, which may be persistent. In some embodiments, a graphics processor is configured to generate a pool of private memory pages for a set of graphics work that includes multiple threads. The processor may maintain a translation table configured to map private memory addresses to virtual addresses based on identifiers of the threads. The processor may execute a mapping thread to receive a request to allocate a private memory page for a requesting thread, select a private memory page from the pool in response to the request, and map the selected page in the translation table for the requesting. The processor may then execute one or more instructions of the requesting thread to access a private memory space, wherein the execution includes translation of a private memory address to a virtual address based on the mapped page in the translation table. The mapping thread may be a persistent thread for which resources are allocated for an entirety of a time interval over which the set of graphics work is executed.

公开(公告)号：US11360780B2

公开(公告)日：2022-06-14

申请号：US16749618

申请日：2020-01-22

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Terence M. Potter ,  Anjana Rajendran ,  Jeffrey T. Brady ,  Brian K. Reynolds ,  Jeffrey A. Lohman

IPC: G06F9/38

Abstract: Techniques are disclosed relating to context switching in a SIMD processor. In some embodiments, an apparatus includes pipeline circuitry configured to execute graphics instructions included in threads of a group of single-instruction multiple-data (SIMD) threads in a thread group. In some embodiments, context switch circuitry is configured to atomically: save, for the SIMD group, a program counter and information that indicates whether threads in the SIMD group are active using one or more context switch registers, set all threads to an active state for the SIMD group, and branch to handler code for the SIMD group. In some embodiments, the pipeline circuitry is configured to execute the handler code to save context information for the SIMD group and subsequently execute threads of another thread group. Disclosed techniques may allow instruction-level context switching even when some SIMD threads are non-active.

公开(公告)号：US20210224072A1

公开(公告)日：2021-07-22

申请号：US16749618

申请日：2020-01-22

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Terence M. Potter ,  Anjana Rajendran ,  Jeffrey T. Brady ,  Brian K. Reynolds ,  Jeffrey A. Lohman

IPC: G06F9/38

Abstract: Techniques are disclosed relating to context switching in a SIMD processor. In some embodiments, an apparatus includes pipeline circuitry configured to execute graphics instructions included in threads of a group of single-instruction multiple-data (SIMD) threads in a thread group. In some embodiments, context switch circuitry is configured to atomically: save, for the SIMD group, a program counter and information that indicates whether threads in the SIMD group are active using one or more context switch registers, set all threads to an active state for the SIMD group, and branch to handler code for the SIMD group. In some embodiments, the pipeline circuitry is configured to execute the handler code to save context information for the SIMD group and subsequently execute threads of another thread group. Disclosed techniques may allow instruction-level context switching even when some SIMD threads are non-active.