公开(公告)号：US09411392B2

公开(公告)日：2016-08-09

申请号：US14295997

申请日：2014-06-04

Applicant: Apple Inc.

Inventor： Ajay Bhatia ,  Michael Dreesen

IPC: G11C7/00 ,  G06F1/32 ,  G11C5/14 ,  G06F12/06 ,  G06F12/02 ,  G11C7/10 ,  G11C11/419

CPC classification number: G06F1/3203 ,  G06F12/0223 ,  G06F12/06 ,  G06F2212/1016 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1096 ,  G11C11/419

Abstract: A system for storing data in a memory may include circuitry that may receive an address, a command and data. The circuitry may also determine a type of the command and generate a read control or write control signal dependent upon the type. The system may also include a plurality of sub-arrays and sense amplifiers. Each of the sub-arrays may include a plurality of memory cells. Each of the sense amplifiers may be coupled to a respective one of the plurality of sub-arrays and may read data stored in a first memory cell included in the respective sub-array. The system may also include one or more write driver circuits. A first write driver circuit may be coupled to at least two of the plurality of sub-arrays. The first write driver circuit may be configured to store data into a second memory cell in one of the at least two sub-arrays.

Abstract translation: 用于将数据存储在存储器中的系统可以包括可以接收地址，命令和数据的电路。 电路还可以确定命令的类型，并根据该类型生成读控制或写控制信号。 该系统还可以包括多个子阵列和感测放大器。 每个子阵列可以包括多个存储单元。 每个读出放大器可以耦合到多个子阵列中的相应一个子阵列，并且可以读取存储在包括在相应子阵列中的第一存储单元中的数据。 该系统还可以包括一个或多个写入驱动器电路。 第一写入驱动器电路可以耦合到多个子阵列中的至少两个。 第一写入驱动器电路可以被配置为将数据存储在至少两个子阵列之一中的第二存储器单元中。

公开(公告)号：US09189052B2

公开(公告)日：2015-11-17

申请号：US14296066

申请日：2014-06-04

Applicant: Apple Inc.

Inventor： Ajay Bhatia ,  Michael Dreesen

IPC: G11C5/14 ,  G06F1/32 ,  G06F12/06 ,  G06F12/02 ,  G11C7/10 ,  G11C11/419

CPC classification number: G06F1/3203 ,  G06F12/0223 ,  G06F12/06 ,  G06F2212/1016 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1096 ,  G11C11/419

Abstract: A system, a voltage regulator and a method for regulating power are disclosed, wherein the system may include a processor, a voltage regulator circuit, and a memory unit. The voltage regulator circuit may be configured to generate a first power supply voltage provided to the memory unit. The voltage regulator circuit may be further configured to adjust a voltage level of two output nodes dependent upon a level of the first power supply voltage and a level of a reference voltage. The voltage regulator circuit may be further configured to adjust the level of the first power supply signal dependent upon the level of at least one of the two output voltages. The voltage regulating circuit may also provide the first output voltage to the second output voltage via an impedance.

Abstract translation: 公开了一种系统，电压调节器和用于调节功率的方法，其中系统可以包括处理器，电压调节器电路和存储器单元。 电压调节器电路可以被配置为产生提供给存储器单元的第一电源电压。 电压调节器电路还可以被配置为根据第一电源电压的电平和参考电压的电平来调整两个输出节点的电压电平。 电压调节器电路还可以被配置为根据两个输出电压中的至少一个的电平来调节第一电源信号的电平。 电压调节电路还可以经由阻抗将第一输出电压提供给第二输出电压。

公开(公告)号：US09411391B2

公开(公告)日：2016-08-09

申请号：US14269841

申请日：2014-05-05

Applicant: Apple Inc.

Inventor： Ajay Bhatia ,  Michael Dreesen

IPC: G06F1/32 ,  G11C5/14 ,  G06F12/06 ,  G06F12/02 ,  G11C7/10 ,  G11C11/419

CPC classification number: G06F1/3203 ,  G06F12/0223 ,  G06F12/06 ,  G06F2212/1016 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1096 ,  G11C11/419

Abstract: A system and method for managing power in a memory, wherein the system may include a processor and a memory unit coupled to the processor. The memory unit may initialize an address decoder into a first power mode. In response to receiving a command and an address corresponding to a location within the memory unit, the memory unit may use the first stage of the address decoder to decode at least a portion of the address. The memory unit may further switch a selected portion of a second stage of the address decoder from the first power mode to the second power mode, wherein the selected portion of the second stage of the address decoder is selected dependent upon an output signal of the first stage of the address decoder.

Abstract translation: 一种用于管理存储器中的电力的系统和方法，其中所述系统可以包括处理器和耦合到所述处理器的存储器单元。 存储单元可以将地址解码器初始化为第一功率模式。 响应于接收到与存储器单元内的位置相对应的命令和地址，存储器单元可以使用地址解码器的第一级来解码地址的至少一部分。 存储器单元还可以将地址解码器的第二级的选定部分从第一功率模式切换到第二功率模式，其中地址解码器的第二级的选择部分取决于第一级的第一级的输出信号 地址解码器的阶段。

公开(公告)号：US20150228312A1

公开(公告)日：2015-08-13

申请号：US14296066

申请日：2014-06-04

Applicant: Apple Inc.

Inventor： Ajay Bhatia ,  Michael Dreesen

IPC: G11C5/14

CPC classification number: G06F1/3203 ,  G06F12/0223 ,  G06F12/06 ,  G06F2212/1016 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1096 ,  G11C11/419

Abstract: A system, a voltage regulator and a method for regulating power are disclosed, wherein the system may include a processor, a voltage regulator circuit, and a memory unit. The voltage regulator circuit may be configured to generate a first power supply voltage provided to the memory unit. The voltage regulator circuit may be further configured to adjust a voltage level of two output nodes dependent upon a level of the first power supply voltage and a level of a reference voltage. The voltage regulator circuit may be further configured to adjust the level of the first power supply signal dependent upon the level of at least one of the two output voltages. The voltage regulating circuit may also provide the first output voltage to the second output voltage via an impedance.

Abstract translation: 公开了一种系统，电压调节器和用于调节功率的方法，其中系统可以包括处理器，电压调节器电路和存储器单元。 电压调节器电路可以被配置为产生提供给存储器单元的第一电源电压。 电压调节器电路还可以被配置为根据第一电源电压的电平和参考电压的电平来调整两个输出节点的电压电平。 电压调节器电路还可以被配置为根据两个输出电压中的至少一个的电平来调节第一电源信号的电平。 电压调节电路还可以经由阻抗将第一输出电压提供给第二输出电压。

公开(公告)号：US20150227456A1

公开(公告)日：2015-08-13

申请号：US14295997

申请日：2014-06-04

Applicant: Apple Inc.

Inventor： Ajay Bhatia ,  Michael Dreesen

IPC: G06F12/02

CPC classification number: G06F1/3203 ,  G06F12/0223 ,  G06F12/06 ,  G06F2212/1016 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1096 ,  G11C11/419

Abstract: A system for storing data in a memory may include circuitry that may receive an address, a command and data. The circuitry may also determine a type of the command and generate a read control or write control signal dependent upon the type. The system may also include a plurality of sub-arrays and sense amplifiers. Each of the sub-arrays may include a plurality of memory cells. Each of the sense amplifiers may be coupled to a respective one of the plurality of sub-arrays and may read data stored in a first memory cell included in the respective sub-array. The system may also include one or more write driver circuits. A first write driver circuit may be coupled to at least two of the plurality of sub-arrays. The first write driver circuit may be configured to store data into a second memory cell in one of the at least two sub-arrays.

Abstract translation: 用于将数据存储在存储器中的系统可以包括可以接收地址，命令和数据的电路。 电路还可以确定命令的类型，并根据该类型生成读控制或写控制信号。 该系统还可以包括多个子阵列和感测放大器。 每个子阵列可以包括多个存储单元。 每个读出放大器可以耦合到多个子阵列中的相应一个子阵列，并且可以读取存储在包括在相应子阵列中的第一存储单元中的数据。 该系统还可以包括一个或多个写入驱动器电路。 第一写入驱动器电路可以耦合到多个子阵列中的至少两个。 第一写入驱动器电路可以被配置为将数据存储在至少两个子阵列之一中的第二存储器单元中。

公开(公告)号：US20150227186A1

公开(公告)日：2015-08-13

申请号：US14269841

申请日：2014-05-05

Applicant: Apple Inc.

Inventor： Ajay Bhatia ,  Michael Dreesen

IPC: G06F1/32 ,  G06F12/06

CPC classification number: G06F1/3203 ,  G06F12/0223 ,  G06F12/06 ,  G06F2212/1016 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1096 ,  G11C11/419

Abstract: A system and method for managing power in a memory, wherein the system may include a processor and a memory unit coupled to the processor. The memory unit may initialize an address decoder into a first power mode. In response to receiving a command and an address corresponding to a location within the memory unit, the memory unit may use the first stage of the address decoder to decode at least a portion of the address. The memory unit may further switch a selected portion of a second stage of the address decoder from the first power mode to the second power mode, wherein the selected portion of the second stage of the address decoder is selected dependent upon an output signal of the first stage of the address decoder.

Abstract translation: 一种用于管理存储器中的电力的系统和方法，其中所述系统可以包括处理器和耦合到所述处理器的存储器单元。 存储单元可以将地址解码器初始化为第一功率模式。 响应于接收到与存储器单元内的位置相对应的命令和地址，存储器单元可以使用地址解码器的第一级来解码地址的至少一部分。 存储器单元还可以将地址解码器的第二级的选定部分从第一功率模式切换到第二功率模式，其中地址解码器的第二级的选择部分取决于第一级的第一级的输出信号 地址解码器的阶段。