Die-to-die dynamic clock and power gating

    公开(公告)号:US11592889B2

    公开(公告)日:2023-02-28

    申请号:US17318670

    申请日:2021-05-12

    Applicant: Apple Inc.

    Abstract: A system includes a plurality of systems-on-a-chip (SoCs), connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on their respective portions of the network. A given one of the plurality of SoCs may be configured to determine that a local condition for placing the respective portion of the network corresponding to the given SoC into a reduced power mode has been satisfied. The given SoC may be further configured to place the respective portion of the network into the reduced power mode in response to determining that a global condition for the reduced power mode is satisfied. The global condition may be assessed based upon current local power information for remaining ones of the plurality of SoCs.

    Die-to-die dynamic clock and power gating

    公开(公告)号:US12248350B2

    公开(公告)日:2025-03-11

    申请号:US18174985

    申请日:2023-02-27

    Applicant: Apple Inc.

    Abstract: A system includes a plurality of systems-on-a-chip (SoCs), connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on their respective portions of the network. A given one of the plurality of SoCs may be configured to determine that a local condition for placing the respective portion of the network corresponding to the given SoC into a reduced power mode has been satisfied. The given SoC may be further configured to place the respective portion of the network into the reduced power mode in response to determining that a global condition for the reduced power mode is satisfied. The global condition may be assessed based upon current local power information for remaining ones of the plurality of SoCs.

    Die-to-die Dynamic Clock and Power Gating
    3.
    发明公开

    公开(公告)号:US20230214350A1

    公开(公告)日:2023-07-06

    申请号:US18174985

    申请日:2023-02-27

    Applicant: Apple Inc.

    CPC classification number: G06F13/4291 G06F9/30083 G06F13/4022

    Abstract: A system includes a plurality of systems-on-a-chip (SoCs), connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on their respective portions of the network. A given one of the plurality of SoCs may be configured to determine that a local condition for placing the respective portion of the network corresponding to the given SoC into a reduced power mode has been satisfied. The given SoC may be further configured to place the respective portion of the network into the reduced power mode in response to determining that a global condition for the reduced power mode is satisfied. The global condition may be assessed based upon current local power information for remaining ones of the plurality of SoCs.

    Die-to-die Dynamic Clock and Power Gating

    公开(公告)号:US20220365579A1

    公开(公告)日:2022-11-17

    申请号:US17318670

    申请日:2021-05-12

    Applicant: Apple Inc.

    Abstract: A system includes a plurality of systems-on-a-chip (SoCs), connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on their respective portions of the network. A given one of the plurality of SoCs may be configured to determine that a local condition for placing the respective portion of the network corresponding to the given SoC into a reduced power mode has been satisfied. The given SoC may be further configured to place the respective portion of the network into the reduced power mode in response to determining that a global condition for the reduced power mode is satisfied. The global condition may be assessed based upon current local power information for remaining ones of the plurality of SoCs.

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