公开(公告)号：US10037073B1

公开(公告)日：2018-07-31

申请号：US15273925

申请日：2016-09-23

Applicant: Apple Inc.

Inventor： Edvin Catovic ,  Rajat Goel ,  Richard F. Russo ,  Matthew R. Johnson ,  Shingo Suzuki ,  Pradeep Kanapathipillai ,  Raghava Rao V. Denduluri ,  Pankaj Lnu

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3243

Abstract: A processor includes an instruction issue circuit, and high-utilization and low-utilization execution unit circuits coupled to execute instructions received from the instruction issue unit. On average, utilization of the low-utilization execution unit circuit is lower than utilization of the high-utilization execution unit circuit. The processor also includes a retention circuit coupled to a different power domain than the low-utilization execution unit circuit, and a power management circuit. The power management circuit may be configured to detect that inactivity of the low-utilization execution unit circuit satisfies a threshold inactivity level; upon detecting that the threshold inactivity level is satisfied, cause architecturally-visible state of the low-utilization execution unit circuit to be copied to the retention circuit; and subsequent to copying of the architecturally-visible state to the retention circuit, cause the low-utilization execution unit circuit to enter a power-off state, where the retention circuit retains stored data during the power-off state.