公开(公告)号：US10438683B2

公开(公告)日：2019-10-08

申请号：US15810166

申请日：2017-11-13

申请人： Apple Inc.

发明人： Barak Sagiv ,  Einav Yogev ,  Eli Yazovitsky ,  Eyal Gurgi ,  Roi Solomon

IPC分类号： G11C29/44 ,  G11C29/38 ,  G11C29/02

摘要： A storage apparatus includes a plurality of memory cells and storage circuitry. The storage circuitry is configured to store a mapping that maps sets of readout bit-flip counts to respective predefined impairment profiles. The impairment profiles specify two or more severity levels of respective impairment types, including read disturb, retention and endurance. Each of the bit-flip counts includes a one-to-zero error count or a zero-to-one error count. The storage circuitry is configured to read data from a group of the memory cells using given readout parameters, to evaluate an actual set of bit-flip counts corresponding to the read data, to classify the group of the memory cells to a respective impairment profile by mapping the actual set of the bit-flip counts using the mapping, and to adapt the readout parameters based on the impairment profile to which the group of the memory cells was classified.

公开(公告)号：US20180075926A1

公开(公告)日：2018-03-15

申请号：US15810166

申请日：2017-11-13

申请人： Apple Inc.

发明人： Barak Sagiv ,  Einav Yogev ,  Eli Yazovitsky ,  Eyal Gurgi ,  Roi Solomon

IPC分类号： G11C29/44 ,  G11C29/38

CPC分类号： G11C29/44 ,  G11C29/028 ,  G11C29/38

摘要： A storage apparatus includes a plurality of memory cells and storage circuitry. The storage circuitry is configured to store a mapping that maps sets of readout bit-flip counts to respective predefined impairment profiles. The impairment profiles specify two or more severity levels of respective impairment types, including read disturb, retention and endurance. Each of the bit-flip counts includes a one-to-zero error count or a zero-to-one error count. The storage circuitry is configured to read data from a group of the memory cells using given readout parameters, to evaluate an actual set of bit-flip counts corresponding to the read data, to classify the group of the memory cells to a respective impairment profile by mapping the actual set of the bit-flip counts using the mapping, and to adapt the readout parameters based on the impairment profile to which the group of the memory cells was classified.

公开(公告)号：US09847141B1

公开(公告)日：2017-12-19

申请号：US15225863

申请日：2016-08-02

申请人： APPLE INC.

发明人： Barak Sagiv ,  Einav Yogev ,  Eli Yazovitsky ,  Eyal Gurgi ,  Roi Solomon

IPC分类号： G06F11/00 ,  G11C29/00 ,  G11C29/44 ,  G11C29/38

CPC分类号： G11C29/44 ,  G11C29/028 ,  G11C29/38

摘要： A storage apparatus includes a plurality of memory cells and storage circuitry. The storage circuitry is configured to store a mapping that maps sets of readout bit-flip counts to respective predefined impairment profiles. The impairment profiles specify two or more severity levels of respective impairment types, including read disturb, retention and endurance. Each of the bit-flip counts includes a one-to-zero error count or a zero-to-one error count. The storage circuitry is configured to read data from a group of the memory cells using given readout parameters, to evaluate an actual set of bit-flip counts corresponding to the read data, to classify the group of the memory cells to a respective impairment profile by mapping the actual set of the bit-flip counts using the mapping, and to adapt the readout parameters based on the impairment profile to which the group of the memory cells was classified.