公开(公告)号：US20190052254A1

公开(公告)日：2019-02-14

申请号：US15676752

申请日：2017-08-14

申请人： Apple Inc.

发明人： Greg M. Hess ,  Hemangi U. Gajjewar ,  Sachmanik Cheema

IPC分类号： H03K5/159 ,  H03K19/0175

摘要： An apparatus for delaying a signal transition is disclosed. The apparatus includes a first circuit coupled to a first power supply signal and a second, different power supply signal. The first circuit may be configured to, based on a voltage level of a logic signal, sink a current from an intermediate circuit node. A value of the current may be based upon a voltage level of the second different power supply signal. The apparatus also includes a second circuit coupled to the first power supply signal. The second circuit may be configured to generate an output signal based upon a voltage level of the intermediate circuit node. An amount of time between a transition of the logic signal and a corresponding transition of the output signal may be based on an amount of the current.

公开(公告)号：US10217494B2

公开(公告)日：2019-02-26

申请号：US15635825

申请日：2017-06-28

申请人： Apple Inc.

发明人： Bharan Giridhar ,  Sachmanik Cheema ,  Greg M. Hess

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C8/12

摘要： A memory that includes multiple banks, each of which include multiple data storage cells, is disclosed. A decoder circuit may be configured to receive and decode information indicative of an address, and select a particular bank based on the decoded information. A first latch circuit coupled to a particular global bit line, which is, in turn, coupled to the particular bank, may generate multiple local clock signals using the decoded information and store data based on a voltage level of the particular global bit line using the plurality of local clock signals. Other circuits may also pre-charge the particular global bit line using a particular local clock signal of the plurality of local clock signals.

公开(公告)号：US10833664B2

公开(公告)日：2020-11-10

申请号：US15676752

申请日：2017-08-14

申请人： Apple Inc.

发明人： Greg M. Hess ,  Hemangi U. Gajjewar ,  Sachmanik Cheema

IPC分类号： H03K5/159 ,  H03K19/0175 ,  H03K5/00 ,  G06F30/30

摘要： An apparatus for delaying a signal transition is disclosed. The apparatus includes a first circuit coupled to a first power supply signal and a second, different power supply signal. The first circuit may be configured to, based on a voltage level of a logic signal, sink a current from an intermediate circuit node. A value of the current may be based upon a voltage level of the second different power supply signal. The apparatus also includes a second circuit coupled to the first power supply signal. The second circuit may be configured to generate an output signal based upon a voltage level of the intermediate circuit node. An amount of time between a transition of the logic signal and a corresponding transition of the output signal may be based on an amount of the current.

公开(公告)号：US20190005993A1

公开(公告)日：2019-01-03

申请号：US15635825

申请日：2017-06-28

申请人： Apple Inc.

发明人： Bharan Giridhar ,  Sachmanik Cheema ,  Greg M. Hess

IPC分类号： G11C7/12 ,  G11C8/12

摘要： A memory that includes multiple banks, each of which include multiple data storage cells, is disclosed. A decoder circuit may be configured to receive and decode information indicative of an address, and select a particular bank based on the decoded information. A first latch circuit coupled to a particular global bit line, which is, in turn, coupled to the particular bank, may generate multiple local clock signals using the decoded information and store data based on a voltage level of the particular global bit line using the plurality of local clock signals. Other circuits may also pre-charge the particular global bit line using a particular local clock signal of the plurality of local clock signals.