MID POWER MODE FOR AN OSCILLATOR
    1.
    发明申请

    公开(公告)号:US20210200258A1

    公开(公告)日:2021-07-01

    申请号:US16080464

    申请日:2017-09-28

    申请人: Apple Inc.

    IPC分类号: G06F1/10 G06F1/324 H03B5/36

    摘要: Methods, systems, and circuitries are provided to generate clock signals of different qualities in a device. A method includes determining whether the device is operating in a mid power mode or a high power mode. In response to determining that the device is operating in the mid power mode, oscillator circuitry is controlled to cause the oscillator circuitry to consume a lower amount of power, such that the oscillator circuitry generates a lower quality clock signal. In response to determining that the device is operating in the high power mode, the oscillator circuitry is controlled to cause the oscillator circuitry to consume a higher amount of power, such that the oscillator circuitry generates a higher quality clock signal. The lower amount of power and the higher amount of power are different from one another.

    Mid power mode for an oscillator
    2.
    发明授权

    公开(公告)号:US11221643B2

    公开(公告)日:2022-01-11

    申请号:US16080464

    申请日:2017-09-28

    申请人: Apple Inc.

    摘要: Methods, systems, and circuitries are provided to generate clock signals of different qualities in a device. A method includes determining whether the device is operating in a mid power mode or a high power mode. In response to determining that the device is operating in the mid power mode, oscillator circuitry is controlled to cause the oscillator circuitry to consume a lower amount of power, such that the oscillator circuitry generates a lower quality clock signal. In response to determining that the device is operating in the high power mode, the oscillator circuitry is controlled to cause the oscillator circuitry to consume a higher amount of power, such that the oscillator circuitry generates a higher quality clock signal. The lower amount of power and the higher amount of power are different from one another.