公开(公告)号：US20240126457A1

公开(公告)日：2024-04-18

申请号：US18535697

申请日：2023-12-11

Applicant: Apple Inc.

Inventor： Rohit Natarajan ,  Jurgen M. Schulz ,  Christopher D. Shuler ,  Rohit K. Gupta ,  Thomas T. Zou ,  Srinivasa Rangan Sridharan

IPC: G06F3/06 ,  G06F12/0831

CPC classification number: G06F3/0631 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0835 ,  G06F2212/1021

Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

公开(公告)号：US11893251B2

公开(公告)日：2024-02-06

申请号：US17462812

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Rohit Natarajan ,  Jurgen M. Schulz ,  Christopher D. Shuler ,  Rohit K. Gupta ,  Thomas T. Zou ,  Srinivasa Rangan Sridharan

IPC: G06F3/06 ,  G06F12/0831

CPC classification number: G06F3/0631 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0835 ,  G06F2212/1021

Abstract: A non-transitory computer-readable medium is disclosed, the medium having instructions stored thereon that are executable by a computer system to perform operations that may include allocating a plurality of storage locations in a system memory of the computer system to a buffer. The operations may further include selecting a particular order for allocating the plurality of storage locations into a cache memory circuit. This particular order may increase a uniformity of cache miss rates in comparison to a linear order. The operations may also include caching subsets of the plurality of storage locations of the buffer using the particular order.

公开(公告)号：US20230062917A1

公开(公告)日：2023-03-02

申请号：US17462812

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Rohit Natarajan ,  Jurgen M. Schulz ,  Christopher D. Shuler ,  Rohit K. Gupta ,  Thomas T. Zou ,  Srinivasa Rangan Sridharan

IPC: G06F3/06 ,  G06F12/0831

Abstract: A non-transitory computer-readable medium is disclosed, the medium having instructions stored thereon that are executable by a computer system to perform operations that may include allocating a plurality of storage locations in a system memory of the computer system to a buffer. The operations may further include selecting a particular order for allocating the plurality of storage locations into a cache memory circuit. This particular order may increase a uniformity of cache miss rates in comparison to a linear order. The operations may also include caching subsets of the plurality of storage locations of the buffer using the particular order.

公开(公告)号：US11704245B2

公开(公告)日：2023-07-18

申请号：US17462777

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Rohit Natarajan ,  Jurgen M. Schulz ,  Christopher D. Shuler ,  Rohit K. Gupta ,  Thomas T. Zou ,  Srinivasa Rangan Sridharan

IPC: G06F12/00 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

公开(公告)号：US20230067307A1

公开(公告)日：2023-03-02

申请号：US17462777

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Rohit Natarajan ,  Jurgen M. Schulz ,  Christopher D. Shuler ,  Rohit K. Gupta ,  Thomas T. Zou ,  Srinivasa Rangan Sridharan

IPC: G06F12/0802

Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.