公开(公告)号：US12235769B2

公开(公告)日：2025-02-25

申请号：US18422584

申请日：2024-01-25

Applicant: Apple Inc.

Inventor： Tyler J. Huberty ,  Vivek Venkatraman ,  Sandeep Gupta ,  Eric J. Furbish ,  Srinivasa Rangan Sridharan ,  Stephen G. Meier

IPC: G06F12/08 ,  G06F9/38 ,  G06F12/02 ,  G06F12/0831 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/126

Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates. Multiple levels of criticality may be available for a given cache line and cache circuitry may adjust the criticality value of in response to a criticality event. One or more upper criticality levels may be masked when selecting a victim cache line for replacement.

公开(公告)号：US20230060225A1

公开(公告)日：2023-03-02

申请号：US17727031

申请日：2022-04-22

Applicant: Apple Inc.

Inventor： Tyler J. Huberty ,  Vivek Venkatraman ,  Sandeep Gupta ,  Eric J. Furbish ,  Srinivasa Rangan Sridharan ,  Stephan G. Meier

IPC: G06F12/0891 ,  G06F12/0862 ,  G06F12/126 ,  G06F9/38

Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.

公开(公告)号：US20250103496A1

公开(公告)日：2025-03-27

申请号：US18433118

申请日：2024-02-05

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Amanvir Singh Sidana ,  Sandeep Gupta ,  Tom Greenshtein ,  Vivek Venkatraman

IPC: G06F12/0817 ,  G06F12/0891

Abstract: An apparatus includes a plurality of coherent agents, and a coherence directory that includes directory ways for storing coherency information. The coherence directory may be configured to determine that a cache block that is not currently cached among the coherent agents, is stored in a first coherent agent. The coherence directory may be further configured to, in response to this determination, create a particular entry in a selected one of the directory ways. The coherence directory may also be configured to send, to the first coherent agent, an indicator identifying a directory way that includes the entry. In response to a second coherent agent caching the cache block, the coherence directory may update the entry to include the second coherent agent. The first and second coherent agents may be configured to receive copies of the indicator, and to store their copy in locations associated with the cache block.

公开(公告)号：US20240168887A1

公开(公告)日：2024-05-23

申请号：US18422584

申请日：2024-01-25

Applicant: Apple Inc.

Inventor： Tyler J. Huberty ,  Vivek Venkatraman ,  Sandeep Gupta ,  Eric J. Furbish ,  Srinivasa Rangan Sridharan ,  Stephen G. Meier

IPC: G06F12/0891 ,  G06F9/38 ,  G06F12/02 ,  G06F12/0831 ,  G06F12/0862 ,  G06F12/126

CPC classification number: G06F12/0891 ,  G06F9/3877 ,  G06F12/0292 ,  G06F12/0833 ,  G06F12/0862 ,  G06F12/126 ,  G06F2212/1021

Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates. Multiple levels of criticality may be available for a given cache line and cache circuitry may adjust the criticality value of in response to a criticality event. One or more upper criticality levels may be masked when selecting a victim cache line for replacement.

公开(公告)号：US11822480B2

公开(公告)日：2023-11-21

申请号：US17727020

申请日：2022-04-22

Applicant: Apple Inc.

Inventor： Tyler J. Huberty ,  Vivek Venkatraman ,  Sandeep Gupta ,  Eric J. Furbish ,  Srinivasa Rangan Sridharan ,  Stephan G. Meier

IPC: G06F12/0891 ,  G06F12/0862 ,  G06F9/38 ,  G06F12/126 ,  G06F12/02 ,  G06F12/0831

CPC classification number: G06F12/0891 ,  G06F9/3877 ,  G06F12/0292 ,  G06F12/0833 ,  G06F12/0862 ,  G06F12/126 ,  G06F2212/1021

Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.

公开(公告)号：US11921640B2

公开(公告)日：2024-03-05

申请号：US17727031

申请日：2022-04-22

Applicant: Apple Inc.

Inventor： Tyler J. Huberty ,  Vivek Venkatraman ,  Sandeep Gupta ,  Eric J. Furbish ,  Srinivasa Rangan Sridharan ,  Stephan G. Meier

IPC: G06F12/08 ,  G06F9/38 ,  G06F12/02 ,  G06F12/0831 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/126

CPC classification number: G06F12/0891 ,  G06F9/3877 ,  G06F12/0292 ,  G06F12/0833 ,  G06F12/0862 ,  G06F12/126 ,  G06F2212/1021

Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.

公开(公告)号：US20230066236A1

公开(公告)日：2023-03-02

申请号：US17727020

申请日：2022-04-22

Applicant: Apple Inc.

Inventor： Tyler J. Huberty ,  Vivek Venkatraman ,  Sandeep Gupta ,  Eric J. Furbish ,  Srinivasa Rangan Sridharan ,  Stephan G. Meier

IPC: G06F12/0891 ,  G06F12/0831 ,  G06F12/126 ,  G06F12/02

Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.