公开(公告)号：US20250063797A1

公开(公告)日：2025-02-20

申请号：US18762053

申请日：2024-07-02

Applicant: Applied Materials, Inc.

Inventor： Kyoung Ha KIM ,  Veeraraghavan S. BASKER ,  Byeong Chan LEE ,  Andrew YEOH

IPC: H01L29/417 ,  H01L21/283 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775 ,  H01L29/786

Abstract: A method of forming a portion of a gate-all-around field-effect transistor includes performing a selective deposition process to form selective cap layers at bottoms of contact trenches formed within portions of a substrate isolated by shallow trench isolations (STIs), wherein the contact trenches each interface with an S/D epitaxial (epi) layer with an extension region, performing a substrate angled etch process to etch sidewalls of the contact trenches, enlarging top critical dimension (CD) of the contact trenches, performing a substrate selective removal plasma (SRP) etch process to isotropically etch the substrate within the contact trenches, performing a recess fill process to fill the contact trenches with dielectric layers, performing an inter-layer dielectric (ILD) recess process to partially remove the substrate between the dielectric layers within the contact trenches and form an ILD recess, and performing a substrate isotropic etch process to partially remove the substrate within the ILD recess.

公开(公告)号：US20220384258A1

公开(公告)日：2022-12-01

申请号：US17728871

申请日：2022-04-25

Applicant: Applied Materials, Inc.

Inventor： Nicolas Louis BREIL ,  Byeong Chan LEE ,  Benjamin COLOMBEAU

IPC: H01L21/768 ,  H01L29/40 ,  H01L29/66 ,  H01L21/285 ,  H01L29/417 ,  H01L23/522

Abstract: A method of forming a contact trench structure in a semiconductor device, the method includes performing a first selective deposition process to form a contact on sidewalls of a trench, each of the sidewalls of the trench comprising a first cross section of a first material and a second cross section of a second material, performing a second selective deposition process to form a metal silicide layer on the contact, performing a first metal fill process to form a contact plug within the trench, the first metal fill process including depositing a contact plug metal material within the trench, performing an etch process to form an opening within the trench, comprising partially etching the contact plug metal material within the trench, and performing a second metal fill process, the second metal fill process comprising depositing the contact plug metal material within the opening.

公开(公告)号：US20220336469A1

公开(公告)日：2022-10-20

申请号：US17688602

申请日：2022-03-07

Applicant: Applied Materials, Inc.

Inventor： Nicolas Louis BREIL ,  Fredrick FISHBURN ,  Byeong Chan LEE

IPC: H01L27/108

Abstract: The present disclosure generally relates to dynamic random access memory (DRAM) devices and to semiconductor fabrication for DRAM devices. Certain embodiments disclosed herein provide an integrated processing system and methods for forming CMOS contact, DRAM array bit line contact (BLC), and storage node structures. The integrated processing system and methods enable deposition of contact and storage node layers with reduced contamination and improved quality, thus reducing leakage current and resistance for the final contact and storage node structures.