-
公开(公告)号:US20240162007A1
公开(公告)日:2024-05-16
申请号:US17984772
申请日:2022-11-10
Applicant: Applied Materials, Inc.
Inventor: Deyang LI , Sunil SRINIVASAN , Yi-Chuan CHOU , Shahid RAUF , Kuan-Ting LIU , Jason A. KENNEY , Chung LIU , Olivier P. JOUBERT , Shreeram Jyoti DASH , Aaron EPPLER , Michael Thomas NICHOLS
IPC: H01J37/32
CPC classification number: H01J37/32174 , H01J37/32128 , H01J37/32146 , H01J2237/3341 , H01J2237/3346
Abstract: Embodiments of the present disclosure generally relate to a system used in a semiconductor device manufacturing process. More specifically, embodiments provided herein generally include apparatus and methods for synchronizing and controlling the delivery of an RF bias signal and a pulsed voltage waveform to one or more electrodes within a plasma processing chamber. The apparatus and methods disclosed herein can be useful to at least minimize or eliminate a microloading effect created while processing small dimension features that have differing densities across various regions of a substrate. The plasma processing methods and apparatus described herein are configured to improve the control of various characteristics of the generated plasma and control an ion energy distribution (IED) of the plasma generated ions that interact with a surface of a substrate during plasma processing. The ability to synchronize and control waveform characteristics of a voltage waveform bias established on a substrate during processing allows for an improved control of the generated plasma and process of forming, for example, high-aspect ratio features in the surface of the substrate by a reactive ion etching process. As a result, greater precision for plasma processing can be achieved, which is described herein in more detail.
-
公开(公告)号:US20230260825A1
公开(公告)日:2023-08-17
申请号:US17670777
申请日:2022-02-14
Applicant: Applied Materials, Inc.
Inventor: He REN , Houssam LAZKANI , Raman GAIRE , Mehul NAIK , Kuan-Ting LIU
IPC: H01L21/74 , H01L23/528 , H01L21/20 , H01L23/535 , H01L21/02
CPC classification number: H01L21/743 , H01L23/5286 , H01L21/2022 , H01L23/535 , H01L21/02016
Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.
-
公开(公告)号:US20250157851A1
公开(公告)日:2025-05-15
申请号:US18835577
申请日:2023-02-13
Applicant: Applied Materials, Inc.
Inventor: He REN , Houssam LAZKANI , Raman GAIRE , Mehul NAIK , Kuan-Ting LIU
IPC: H01L21/74 , H01L21/02 , H01L23/528 , H01L23/535
Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 seem to approximately 90 seem in a chamber pressure of approximately 1 Torr to approximately 100 Torr.
-
-