公开(公告)号：US20230260825A1

公开(公告)日：2023-08-17

申请号：US17670777

申请日：2022-02-14

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Houssam LAZKANI ,  Raman GAIRE ,  Mehul NAIK ,  Kuan-Ting LIU

IPC: H01L21/74 ,  H01L23/528 ,  H01L21/20 ,  H01L23/535 ,  H01L21/02

CPC classification number: H01L21/743 ,  H01L23/5286 ,  H01L21/2022 ,  H01L23/535 ,  H01L21/02016

Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.

公开(公告)号：US20240363354A1

公开(公告)日：2024-10-31

申请号：US18636449

申请日：2024-04-16

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Raman GAIRE ,  Shi YOU ,  Pranav RAMESH ,  Houssam LAZKANI ,  Shawn THOMAS ,  Abhishek DUBE ,  Mehul B. NAIK ,  Songkram Sonny SRIVATHANAKUL

IPC: H01L21/285 ,  C30B25/18 ,  C30B29/06 ,  C30B29/68 ,  H01L21/768 ,  H01L29/40

CPC classification number: H01L21/28518 ,  C30B25/18 ,  C30B29/06 ,  C30B29/68 ,  H01L21/768 ,  H01L29/401

Abstract: Semiconductor devices and methods for manufacturing the same are provided. The method includes epitaxially growing a doped crystalline silicon-containing layer over a source/drain feature and growing a doped amorphous silicon-containing layer over a field region of a semiconductor layer. The trench is formed in the semiconductor layer and the trench exposes the source/drain feature. The method further includes epitaxially growing an undoped crystalline silicon-containing capping layer over the doped crystalline silicon-containing layer and growing an undoped amorphous silicon-containing layer over the doped silicon-containing amorphous layer. The method further includes selectively removing the doped amorphous silicon-containing layer and the undoped amorphous silicon-containing layer relative to the silicon-containing crystalline capping layer. The method further includes removing the silicon-containing crystalline capping layer to expose the doped silicon-containing crystalline layer.

公开(公告)号：US20240363345A1

公开(公告)日：2024-10-31

申请号：US18441352

申请日：2024-02-14

Applicant: Applied Materials, Inc.

Inventor： Chang Seok KANG ,  Raman GAIRE ,  Hsueh Chung CHEN ,  In Soo JUNG ,  Houssam LAZKANI ,  Balasubramanian PRANATHARTHIHARAN

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/306

CPC classification number: H01L21/02645 ,  H01L21/02532 ,  H01L21/2003 ,  H01L21/306

Abstract: A method for manufacturing a memory device includes depositing a seed layer in a memory hole extending through a memory stack. The seed layer includes particles, such as silicon particles. The seed layer is etched to produce etched particles. The etched particles act as nuclei for the growth of a crystalline channel material in the memory hole.

公开(公告)号：US20250157851A1

公开(公告)日：2025-05-15

申请号：US18835577

申请日：2023-02-13

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Houssam LAZKANI ,  Raman GAIRE ,  Mehul NAIK ,  Kuan-Ting LIU

IPC: H01L21/74 ,  H01L21/02 ,  H01L23/528 ,  H01L23/535

Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 seem to approximately 90 seem in a chamber pressure of approximately 1 Torr to approximately 100 Torr.

公开(公告)号：US20240282809A1

公开(公告)日：2024-08-22

申请号：US18171090

申请日：2023-02-17

Applicant: Applied Materials, Inc.

Inventor： Amirhasan NOURBAKHSH ,  Raman GAIRE ,  Pei LIU ,  Tyler SHERWOOD ,  Ryan Scott SMITH ,  Roger QUON ,  Siddarth KRISHNAN

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66477

Abstract: A super junction device with an increased voltage rating may be formed by decreasing the width of the P-type region and increasing the doping concentration, while also increasing the height of the overall device. However, instead of etching a trench in the N-type material to fill with the P-type material, a trench may be etched for both the P-type region and an adjacent N-type region. This allows the height of the overall device to be increased while maintaining a feasible aspect ratio for the trench. The P-type material may then be formed as a sidewall liner on the trench that is relatively thin compared to the remaining width of the trench. The trench may then be filled with N-type material such that the P-type region fills the space between the N-type regions without any voids or seams, while having a width that would be unattainable using traditional etch-and-fill methods for the P-type region alone.