公开(公告)号：US11056406B2

公开(公告)日：2021-07-06

申请号：US16688811

申请日：2019-11-19

Applicant: Applied Materials, Inc.

Inventor： Liyan Miao ,  Chentsau Ying ,  Xinhai Han ,  Long Lin

IPC: H01L51/00 ,  H01L21/66 ,  H01L21/02 ,  H01L21/3205 ,  C23C16/40 ,  C23C16/52 ,  C23C16/34 ,  C23C16/24 ,  C23C16/452 ,  H01J37/32 ,  C23C16/54 ,  H01L21/683 ,  C23C16/455 ,  C23C16/509 ,  H01L21/677 ,  H01L21/67

Abstract: Embodiments of the present technology may include a method of forming a stack of semiconductor layers. The method may include depositing a first silicon oxide layer on a substrate. The method may also include depositing a first silicon layer on the first silicon oxide layer. The method may include depositing a first silicon nitride layer on the first silicon layer. The method may further include depositing a second silicon layer on the first silicon nitride layer. In addition, the method may include depositing a stress layer on a side of the substrate opposite a side of the substrate with the first silicon oxide layer. The operations may form a structure of semiconductor layers, where the structure includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, the second silicon layer, the substrate, and the stress layer. Other methods of reducing stress are described.

公开(公告)号：US20190013250A1

公开(公告)日：2019-01-10

申请号：US16026598

申请日：2018-07-03

Applicant: Applied Materials, Inc.

Inventor： Liyan Miao ,  Chentsau Ying ,  Xinhai Han ,  Long Lin

IPC: H01L21/66 ,  H01L21/02 ,  H01L21/3205 ,  C23C16/52 ,  C23C16/34 ,  C23C16/24 ,  C23C16/40

Abstract: Embodiments of the present technology may include a method of forming a stack of semiconductor layers. The method may include depositing a first silicon oxide layer on a substrate. The method may also include depositing a first silicon layer on the first silicon oxide layer. The method may further include depositing a first silicon nitride layer on the first silicon layer. Depositing the first silicon nitride layer or a stress layer may include reducing stress in at least one of the first silicon layer, the first silicon oxide layer, or the substrate. In addition, the method may include depositing a second silicon layer on the first silicon nitride layer. The operations may form the stack of semiconductor layers, where the stack includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, and the second silicon layer.

公开(公告)号：US20200091019A1

公开(公告)日：2020-03-19

申请号：US16688811

申请日：2019-11-19

Applicant: Applied Materials, Inc.

Inventor： Liyan Miao ,  Chentsau Ying ,  Xinhai Han ,  Long Lin

IPC: H01L21/66 ,  H01L21/02 ,  H01L21/3205 ,  C23C16/40 ,  C23C16/52 ,  C23C16/34 ,  C23C16/24 ,  C23C16/452 ,  H01J37/32 ,  H01L51/00 ,  C23C16/54 ,  H01L21/683 ,  C23C16/455 ,  C23C16/509

Abstract: Embodiments of the present technology may include a method of forming a stack of semiconductor layers. The method may include depositing a first silicon oxide layer on a substrate. The method may also include depositing a first silicon layer on the first silicon oxide layer. The method may include depositing a first silicon nitride layer on the first silicon layer. The method may further include depositing a second silicon layer on the first silicon nitride layer. In addition, the method may include depositing a stress layer on a side of the substrate opposite a side of the substrate with the first silicon oxide layer. The operations may form a structure of semiconductor layers, where the structure includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, the second silicon layer, the substrate, and the stress layer. Other methods of reducing stress are described.