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公开(公告)号：US20240107764A1
公开(公告)日：2024-03-28
申请号：US18243085
申请日：2023-09-06
Applicant: Applied Materials, Inc.
Inventor： Milan PESIC
Abstract: Embodiments of the disclosure provided herein include an apparatus for and method of forming an improved three-dimension (3D) memory structure/cell that includes a channel that includes polysilicon channel that has been processed to passivate and remove defects found in the channel structure of a 3D memory device, such as a 3D NAND device. In some embodiments, the processing performed on the channel structure utilizes the deposition of a fluorine containing layer that includes a concentration of fluorine (F) atoms that are then driven into a polysilicon channel layer using at least one anneal step that is performed in a hydrogen or deuterium containing environment to load the polysilicon layer with fluorine (F) and hydrogen (H) atoms.
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公开(公告)号：US20240401189A1
公开(公告)日：2024-12-05
申请号：US18671184
申请日：2024-05-22
Applicant: Applied Materials, Inc.
Inventor： Hsiang Yu LEE , Changwoo SUN , Milan PESIC , Pradeep SUBRAHMANYAN
Abstract: Disclosed are approaches for to fabricating memory device channel holes using a doped film layer. One approach may include providing a substrate and forming a vertical stack over the substrate, wherein the vertical stack includes a plurality of alternating material layers. The method may further include forming a channel hole through the vertical stack, forming an oxide-nitride-oxide layer along a sidewall of the channel hole, forming a silicon layer over the oxide-nitride-oxide layer, forming an etch stop layer over the silicon layer, forming a fluorine-doped silicon layer over the etch step layer, and annealing the vertical stack.
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公开(公告)号：US20240081063A1
公开(公告)日：2024-03-07
申请号：US18447457
申请日：2023-08-10
Applicant: Applied Materials, Inc.
Inventor： Milan PESIC , Pradeep K. SUBRAHMANYAN
Abstract: Embodiments of the disclosure include an apparatus and method of forming an improved memory device. In some embodiments, the apparatus generally includes, for example, a plurality of alternating layers formed over a surface of a substrate including a plurality of word line layers with gate regions and a plurality of inter-word line dielectric layers; a channel; and an ONO layer stack disposed between the gate regions and the channel. The embodiments of the present disclosure may include at least one of: word line layers with gate regions that have sidewalls that have a reverse dome shape, sacrificial layers disposed between the word line layers and the inter-word line dielectric layers, or top and bottom dielectric layers deposited on top and bottom portions of the word line layers. Embodiments of the disclosure described herein may allow for the electric field of the gate regions of a memory device to be modified.
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4.发明公开公开(公告)号：US20230380165A1
公开(公告)日：2023-11-23
申请号：US18198043
申请日：2023-05-16
Applicant: Applied Materials, Inc.
Inventor： Milan PESIC
Abstract: Embodiments of the disclosure include an apparatus and method of forming a memory device with high-mobility oxide semiconductor channels. In some embodiments, the apparatus, for example, includes a plurality of alternating layers formed over a surface of a substrate; a gate coupled to each of the word line layers of the plurality of alternating layers; a multi-layer channel memory cell having a first end coupled to a source region, a second end coupled to a drain region, and extending in the first direction between the source region and the drain region, the multi-layer channel also having a first conductive layer and a second conductive layer, the first conductive layer being different from the second conductive layer; and an ONO layer stack disposed between the gates and the multi-layer channel, wherein the ONO layer stack extends in the first direction between the source region and the drain region.
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