公开(公告)号：US20240186178A1

公开(公告)日：2024-06-06

申请号：US18523401

申请日：2023-11-29

Applicant: Applied Materials, Inc.

Inventor： HsiangYu LEE ,  Pradeep SUBRAHMANYAN ,  Changwoo SUN

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76816 ,  H01L21/76831 ,  H01L23/5226

Abstract: Disclosed are approaches for direct wordline contact formation for 3-D NAND devices. One method may include providing a film stack including a plurality of alternating first layers and second layers, and forming a plurality of contact openings in the film stack, wherein each contact opening is formed to a different etch depth relative to an upper surface of the film stack. The method may further include depositing a liner over the film stack including within each of the contact openings, removing the first layers to form a plurality of wordline openings in the film stack, and forming a plurality of wordlines by depositing a first conductive material within the wordline openings. The method may further include removing the liner from a bottom of each contact opening, and depositing a second conductive material within the contact openings to form a plurality of wordline contacts.

公开(公告)号：US20240185893A1

公开(公告)日：2024-06-06

申请号：US18525198

申请日：2023-11-30

Applicant: Applied Materials, Inc.

Inventor： HsiangYu LEE ,  Pradeep SUBRAHMANYAN ,  Changwoo SUN

IPC: G11C5/06 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

CPC classification number: G11C5/063 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

Abstract: Disclosed are approaches for direct wordline contact formation for 3D NAND devices. One method may include providing a first film stack comprising a first plurality of alternating first layers and second layers, and forming a first plurality of contact openings in the first film stack, wherein each contact opening is formed to a different etch depth. The method may further include forming a sacrificial gapfill within the first plurality of contact openings, and forming a second film stack atop the first film stack, wherein the second film stack comprises a second plurality of alternating first layers and second layers. The method may further include forming a second plurality of contact openings in the second film stack, wherein a first set of contact openings of the second plurality of contact openings extends to the sacrificial gapfill, and removing the sacrificial gapfill from the first plurality of contact openings.

公开(公告)号：US20250140567A1

公开(公告)日：2025-05-01

申请号：US18498813

申请日：2023-10-31

Applicant: Applied Materials, Inc.

Inventor： Stanislav S. TODOROV ,  Wonjae LEE ,  Pradeep SUBRAHMANYAN ,  D. Jeffrey LISCHER

IPC: H01L21/3115 ,  H01J37/24 ,  H01J37/317

Abstract: A a method of stress management in a substrate. The method may include providing a stress compensation layer on a main surface of the substrate; and performing a chained implant procedure to implant a set of ions into the stress compensation layer. The chained implant procedure may include directing a first implant procedure to the substrate, the first implant procedure generating a first damage profile within the stress compensation layer; directing a second implant to the substrate, different from the first implant, wherein a composite damage profile is generated within the stress compensation layer after the second implant, the composite damage profile resulting in a higher stress response ratio than the first damage profile.

公开(公告)号：US20240188300A1

公开(公告)日：2024-06-06

申请号：US18525633

申请日：2023-11-30

Applicant: Applied Materials, Inc.

Inventor： HsiangYu LEE ,  Pradeep SUBRAHMANYAN ,  Changwoo SUN

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35

Abstract: Disclosed are approaches for fabricating 3D NAND flash memory structures including hollow epitaxial channels. One approach for fabricating a 3D NAND memory structure may include forming a plurality of alternating material layers arranged in a vertical stack on a substrate, etching a channel hole that extends through the plurality of alternating material layers to the substrate, and forming a tunneling layer around the channel hole contacting the plurality of alternating material layers. The method may further include forming a channel liner along the tunneling layer, forming a core gap material within the channel liner, removing the channel liner from the channel hole, and epitaxially growing a hollow epitaxial silicon core from the substrate through the channel hole, between the tunneling layer and the core gap material.

公开(公告)号：US20250140523A1

公开(公告)日：2025-05-01

申请号：US18498970

申请日：2023-10-31

Applicant: Applied Materials, Inc.

Inventor： Stanislav S. TODOROV ,  D. Jeffrey LISCHER ,  Wonjae LEE ,  Pradeep SUBRAHMANYAN

IPC: H01J37/317 ,  H01J37/304

Abstract: A method of stress management in a substrate. The method may include comprising providing a stress compensation layer on a main surface of the substrate; and performing a dynamic implant procedure in an ion implanter to implant a set of ions into the stress compensation layer. The dynamic implant procedure may include exposing the substrate to an ion beam under a first set of conditions, the first set of conditions comprising an ion energy, a beam scan rate and a substrate scan rate; and varying at least the ion energy while the substrate is exposed to the ion beam. As such, a stress state of the substrate may change as a function of location on the substrate as a result of the dynamic implant.

公开(公告)号：US20240401189A1

公开(公告)日：2024-12-05

申请号：US18671184

申请日：2024-05-22

Applicant: Applied Materials, Inc.

Inventor： Hsiang Yu LEE ,  Changwoo SUN ,  Milan PESIC ,  Pradeep SUBRAHMANYAN

IPC: C23C16/04 ,  C23C16/24 ,  C23C16/34 ,  C23C16/40

Abstract: Disclosed are approaches for to fabricating memory device channel holes using a doped film layer. One approach may include providing a substrate and forming a vertical stack over the substrate, wherein the vertical stack includes a plurality of alternating material layers. The method may further include forming a channel hole through the vertical stack, forming an oxide-nitride-oxide layer along a sidewall of the channel hole, forming a silicon layer over the oxide-nitride-oxide layer, forming an etch stop layer over the silicon layer, forming a fluorine-doped silicon layer over the etch step layer, and annealing the vertical stack.

公开(公告)号：US20220359208A1

公开(公告)日：2022-11-10

申请号：US17735830

申请日：2022-05-03

Applicant: Applied Materials, Inc.

Inventor： Sankuei LIN ,  Pradeep SUBRAHMANYAN

IPC: H01L21/285 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Methods of forming a nanosheet field effect transistor (FET) device with reduced source/drain contact resistance are provided herein. In some embodiments, a method of forming an FET device includes: etching a nanosheet stack of the nanosheet FET device to form a plurality of first source/drain regions and a plurality of second source/drain regions, the nanosheet stack comprising alternating layers of nanosheet channel layers and sacrificial nanosheet layers; depositing a silicide layer in the plurality of first source/drain regions at ends of the nanosheet channel layers via a selective silicidation process to control a length of the nanosheet channel layers between the first source/drain regions; and performing a metal fill process to fill the plurality of first source/drain regions, wherein the metal fill extends from a lowermost nanosheet channel layer to above an uppermost nanosheet channel layer to facilitate the reduced source/drain contact resistance.