SELECTIVE HARDMASK ETCH FOR SEMICONDUCTOR PROCESSING

    公开(公告)号:US20250118557A1

    公开(公告)日:2025-04-10

    申请号:US18481904

    申请日:2023-10-05

    Abstract: Methods of semiconductor processing may include forming plasma effluents of a hydrogen-and-fluorine-containing precursor. The plasma effluents may then contact a silicon-containing hardmask material and a photoresist material. The silicon-containing hardmask material can overlay an organic material overlaying a substrate in a processing region of a semiconductor processing chamber. Etching the silicon-containing hardmask material with the plasma effluents while the photoresist material with the plasma effluents. The silicon-containing hardmask material can be etched at a selectivity greater than or about 10 relative to the photoresist material. A temperature in the processing region can be maintained at about −20° C. or less.

    BOW MITIGATION IN HIGH ASPECT RATIO OXIDE AND NITRIDE ETCHES

    公开(公告)号:US20250118570A1

    公开(公告)日:2025-04-10

    申请号:US18482384

    申请日:2023-10-06

    Abstract: Methods of semiconductor processing may include forming plasma effluents. The plasma effluents may then contact a carbon-containing hardmask and an oxide cap. The plasma effluents can etch one or more features in the oxide cap through one or more apertures of the carbon-containing hardmask. Etching can create a tapered profile for one or more features in the oxide cap. The one or more features can be characterized by a critical dimension at the bottom of the one or more features. The critical dimension can be less than or about 80% of a width of the one or more apertures.

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