公开(公告)号：US20030228746A1

公开(公告)日：2003-12-11

申请号：US10170128

申请日：2002-06-11

申请人： Applied Materials, Inc.

发明人： Wei Ti Lee ,  Ted Guo

IPC分类号： H01L021/3205 ,  H01L021/4763

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76882

摘要： The present invention relates to a method for depositing metal layers on substrates with improved surface morphology. According to one aspect of the invention, a metal is deposited by chemical vapor deposition on a substrate having an aperture formed therein. A metal is then deposited on the substrate by physical vapor deposition performed with a low substrate temperature. The substrate is then heated. The substrate may then receive a metal deposited by physical vapor deposition performed at a high temperature and an additional heating step. The aperture of the resulting substrate is filled with metal and is substantially void-free and has a smooth surface morphology.

摘要翻译： 本发明涉及一种在具有改进的表面形态的基底上沉积金属层的方法。 根据本发明的一个方面，通过化学气相沉积将金属沉积在其上形成有孔的基底上。 然后通过在低衬底温度下进行的物理气相沉积将金属沉积在衬底上。 然后将基材加热。 然后，基板可以接收通过在高温和附加加热步骤进行的物理气相沉积沉积的金属。 所得衬底的孔径被填充金属，并且基本上无空隙并且具有光滑的表面形态。

公开(公告)号：US20030161943A1

公开(公告)日：2003-08-28

申请号：US10367214

申请日：2003-02-13

申请人： Applied Materials, Inc.

发明人： Liang-Yuh Chen ,  Ted Guo ,  Roderick Craig Mosley ,  Fusen Chen

IPC分类号： B05D005/12 ,  C23C016/00

CPC分类号： H01L21/28562 ,  H01L21/76879

摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates selective chemical vapor deposition aluminum (CVD Al) via fill with a metal wire, preferably copper, formed within a barrier layer. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

公开(公告)号：US20020102842A1

公开(公告)日：2002-08-01

申请号：US10074938

申请日：2002-02-11

申请人： Applied Materials, Inc.

发明人： Roderick Craig Mosley ,  Hong Zhang ,  Fusen Chen ,  Ted Guo ,  Liang-Yun Chen

IPC分类号： H01L021/44 ,  H01L021/4763

CPC分类号： H01L21/76876 ,  C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879

摘要： The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.