VIA SHAPING BETWEEN METAL LAYERS FOR CONTROLLED RESISTANCE

    公开(公告)号:US20250140604A1

    公开(公告)日:2025-05-01

    申请号:US18497096

    申请日:2023-10-30

    Abstract: This disclosure describes structures and methods for forming tapered vias between features in metal layers in semiconductor devices. Instead of straight vias that have 90° vertical sidewalls and a constant cross-sectional area throughout the height of the via, tapered vias may be formed that extend outward from one metal layer to a lower metal layer. The via may be allowed to expand in size in a direction parallel to the feature in the lower metal layer, while remaining a constant width so as not to expand beyond the footprint of the lower feature. This tapered shape results in a larger cross-sectional area at the interface between the via and the lower feature. This lowers the resistance of the via by increasing area for current flow, while also increasing the area of any liners which typically have higher resistances.

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