公开(公告)号：US20240281584A1

公开(公告)日：2024-08-22

申请号：US18170335

申请日：2023-02-16

Applicant: Applied Materials, Inc.

Inventor： Martinus Maria Berkens ,  Bhuvaneshwari Ayyagari ,  Simon Johannes Klaver ,  Vinod Reddy ,  Rene Gerardus Maria Beugels ,  Andres Llopis Lozano

IPC: G06F30/337 ,  G06F30/392

CPC classification number: G06F30/337 ,  G06F30/392

Abstract: A method of automatically generating standard cells may include receiving a definition of a circuit for a standard cell. The definition may include one or more semiconductor devices. The method may also include identifying a plurality of slices that implement a device in the one or more semiconductor devices. Each of the plurality of slices may include a partial layout for the device. The method may further include combining more than one of the plurality of slices into a combined layout to implement the device when forming the standard cell.

公开(公告)号：US20250140604A1

公开(公告)日：2025-05-01

申请号：US18497096

申请日：2023-10-30

Applicant: Applied Materials, Inc.

Inventor： Sefa Dag ,  El Mehdi Bazizi ,  Martinus Maria Berkens ,  Steven Sherman ,  Vinod Reddy

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/64

Abstract: This disclosure describes structures and methods for forming tapered vias between features in metal layers in semiconductor devices. Instead of straight vias that have 90° vertical sidewalls and a constant cross-sectional area throughout the height of the via, tapered vias may be formed that extend outward from one metal layer to a lower metal layer. The via may be allowed to expand in size in a direction parallel to the feature in the lower metal layer, while remaining a constant width so as not to expand beyond the footprint of the lower feature. This tapered shape results in a larger cross-sectional area at the interface between the via and the lower feature. This lowers the resistance of the via by increasing area for current flow, while also increasing the area of any liners which typically have higher resistances.