公开(公告)号：US20240234209A1

公开(公告)日：2024-07-11

申请号：US18544812

申请日：2023-12-19

Applicant: Applied Materials, Inc.

Inventor： Avgerinos V. Gelatos ,  Yang Hu ,  Thomas Anthony Empante ,  Gaurav Thareja ,  Joung Joo Lee ,  Shi You ,  Pranav Ramesh ,  Chi H. Ching ,  Nicolas Breil

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L21/76889 ,  H01L21/823871 ,  H01L23/5283 ,  H01L23/53266 ,  H01L27/0922 ,  H01L29/41725 ,  H01L29/456

Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor. The substrate is pre-cleaned. A molybdenum silicide (MoSi) layer is deposited on one or more of the p transistor and the n transistor. A titanium silicide (TiSi) layer is formed on the n transistor and the p transistor. A capping layer may be formed on the titanium silicide (TiSi) layer. The method may be an integrated method performed in a processing chamber without breaking vacuum.