公开(公告)号：US11978635B2

公开(公告)日：2024-05-07

申请号：US17197871

申请日：2021-03-10

Applicant: Applied Materials, Inc.

Inventor： Swaminathan Srinivasan ,  Abhijit Basu Mallick ,  Nicolas Breil

IPC: H01L21/285 ,  C23C14/04 ,  C23C16/04 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28562 ,  C23C14/042 ,  C23C16/042 ,  H01L21/02208 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/76864 ,  H01L21/76889 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods for forming silicide films are disclosed. Methods of selectively depositing metal-containing films on silicon surfaces which are further processed to form silicide films are disclosed. Specific embodiments of the disclosure relate to the formation of silicide films on FinFET structures without the formation of a metal layer on the dielectric.

公开(公告)号：US20230307506A1

公开(公告)日：2023-09-28

申请号：US18121718

申请日：2023-03-15

Applicant: Applied Materials, Inc.

Inventor： Nicolas Breil ,  Matthew Cogorno ,  Anchuan Wang ,  Byeong Chan Lee ,  Manoj Vellaikal

IPC: H01L29/40 ,  H01L21/3065 ,  C23C16/24 ,  C23C16/56 ,  C23C16/52

CPC classification number: H01L29/401 ,  H01L21/3065 ,  C23C16/24 ,  C23C16/56 ,  C23C16/52 ,  H01L29/45

Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises non-selectively depositing an amorphous silicon layer on a top surface and a sidewall surface of at least one contact trench on a substrate and a crystalline silicon layer on a bottom surface of the at least one contact trench at a temperature less than or equal to 400° C., the bottom surface including a source/drain material. The amorphous silicon layer is selectively removed from the top surface and the sidewall surface at a temperature less than or equal to 400° C. The method may be performed in a processing chamber without breaking vacuum.

公开(公告)号：US20210202256A1

公开(公告)日：2021-07-01

申请号：US17197871

申请日：2021-03-10

Applicant: Applied Materials, Inc.

Inventor： Swaminathan Srinivasan ,  Abhijit Basu Mallick ,  Nicolas Breil

IPC: H01L21/285 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/28 ,  C23C16/04 ,  C23C14/04

Abstract: Methods for forming silicide films are disclosed. Methods of selectively depositing metal-containing films on silicon surfaces which are further processed to form silicide films are disclosed. Specific embodiments of the disclosure relate to the formation of silicide films on FinFET structures without the formation of a metal layer on the dielectric.

公开(公告)号：US10607841B2

公开(公告)日：2020-03-31

申请号：US16220816

申请日：2018-12-14

Applicant: Applied Materials, Inc.

Inventor： Swaminathan Srinivasan ,  Abhijit Basu Mallick ,  Nicolas Breil

IPC: H01L21/285 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/28 ,  C23C16/04 ,  C23C14/04

Abstract: Methods for forming silicide films are disclosed. Methods of selectively depositing metal-containing films on silicon surfaces which are further processed to form silicide films are disclosed. Specific embodiments of the disclosure relate to the formation of silicide films on FinFET structures without the formation of a metal layer on the dielectric.

公开(公告)号：US20240332388A1

公开(公告)日：2024-10-03

申请号：US18609650

申请日：2024-03-19

Applicant: Applied Materials, Inc.

Inventor： Byeong Chan Lee ,  Benjamin Colombeau ,  Nicolas Breil ,  Ashish Pal ,  El Mehdi Bazizi ,  Veeraraghavan S. Basker ,  Balasubramanian Pranatharthiharan ,  Pratik B. Vyas ,  Gregory Costrini

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: One or more embodiments of the disclosure are directed to methods of forming semiconductor devices, e.g., gate-all-around (GAA) transistors that are used in FEOL and/or BEOL processes. The processes described herein may be integrated and performed in any suitable cluster tool. Some embodiments of the disclosure are directed to cavity shaping processes. Further embodiments of the disclosure are directed to logic transistors with wrap-around backside source/drain contact.

公开(公告)号：US20240234209A1

公开(公告)日：2024-07-11

申请号：US18544812

申请日：2023-12-19

Applicant: Applied Materials, Inc.

Inventor： Avgerinos V. Gelatos ,  Yang Hu ,  Thomas Anthony Empante ,  Gaurav Thareja ,  Joung Joo Lee ,  Shi You ,  Pranav Ramesh ,  Chi H. Ching ,  Nicolas Breil

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L21/76889 ,  H01L21/823871 ,  H01L23/5283 ,  H01L23/53266 ,  H01L27/0922 ,  H01L29/41725 ,  H01L29/456

Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor. The substrate is pre-cleaned. A molybdenum silicide (MoSi) layer is deposited on one or more of the p transistor and the n transistor. A titanium silicide (TiSi) layer is formed on the n transistor and the p transistor. A capping layer may be formed on the titanium silicide (TiSi) layer. The method may be an integrated method performed in a processing chamber without breaking vacuum.

公开(公告)号：US20230044391A1

公开(公告)日：2023-02-09

申请号：US17879091

申请日：2022-08-02

Applicant: Applied Materials, Inc.

Inventor： Nicolas Breil ,  Chang Seok Kang

IPC: H01L27/108

Abstract: Described are memory devices having a metal silicide, resulting in a low resistance contact. Methods of forming a memory device are described. The methods include forming a metal silicide layer on a semiconductor material layer on a memory stack, the semiconductor material layer having a capacitor side and a bit line side. A capacitor is then formed on the capacitor side of the metal silicide layer, and a bit line is formed on the bit line side of the metal silicide layer.

公开(公告)号：US20190189453A1

公开(公告)日：2019-06-20

申请号：US16220816

申请日：2018-12-14

Applicant: Applied Materials, Inc.

Inventor： Swaminathan Srinivasan ,  Abhijit Basu Mallick ,  Nicolas Breil

IPC: H01L21/285 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28518 ,  H01L21/02208 ,  H01L21/28562 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods for forming silicide films are disclosed. Methods of selectively depositing metal-containing films on silicon surfaces which are further processed to form silicide films are disclosed. Specific embodiments of the disclosure relate to the formation of silicide films on FinFET structures without the formation of a metal layer on the dielectric.

公开(公告)号：US20240128355A1

公开(公告)日：2024-04-18

申请号：US18378850

申请日：2023-10-11

Applicant: Applied Materials, Inc.

Inventor： Nicolas Breil ,  Byeong Chan Lee

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a source region and a drain region adjacent to a superlattice structure on a substrate. The source region and the drain region comprise a metallic silicide material. In some embodiments, a sacrificial material is first deposited and then removed to form a metallic silicide material in the source and drain region.

公开(公告)号：US10950450B2

公开(公告)日：2021-03-16

申请号：US16836858

申请日：2020-03-31

Applicant: Applied Materials, Inc.

Inventor： Swaminathan Srinivasan ,  Abhijit Basu Mallick ,  Nicolas Breil

IPC: H01L21/285 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/28 ,  C23C16/04 ,  C23C14/04

Abstract: Methods for forming silicide films are disclosed. Methods of selectively depositing metal-containing films on silicon surfaces which are further processed to form silicide films are disclosed. Specific embodiments of the disclosure relate to the formation of silicide films on FinFET structures without the formation of a metal layer on the dielectric.