公开(公告)号：US20240186181A1

公开(公告)日：2024-06-06

申请号：US18074335

申请日：2022-12-02

Applicant: Applied Materials, Inc.

Inventor： Ge QU ,  Qihao ZHU ,  Zheng JU ,  Yang ZHOU ,  Jiajie CEN ,  Feng Q. LIU ,  Zhiyuan WU ,  Feng CHEN ,  Kevin KASHEFI ,  Xianmin TANG ,  Jeffrey W. ANTHIS ,  Mark Joseph SALY

IPC: H01L21/768 ,  H01L21/3205

CPC classification number: H01L21/76849 ,  H01L21/32051 ,  H01L21/76877

Abstract: Methods to deposit a metal cap for an interconnect are disclosed. In embodiments, a method comprises contacting the substrate with an alkyl halide and a ruthenium metal precursor to form a metal cap for an interconnect.

公开(公告)号：US20240290655A1

公开(公告)日：2024-08-29

申请号：US18115561

申请日：2023-02-28

Applicant: Applied Materials, Inc.

Inventor： Zheng JU ,  Zhiyuan WU ,  Jiajie CEN ,  Feng Q. LIU ,  Feng CHEN

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76844 ,  H01L21/76846 ,  H01L21/76879 ,  H01L23/5226 ,  H01L21/76862 ,  H01L23/53238 ,  H01L23/53266

Abstract: A method of selectively filling a via with a simultaneous liner deposition in a semiconductor structure includes forming a passivation layer selectively on an exposed surface of a conductive layer within a via formed in a dielectric layer formed over the conductive layer, forming a barrier layer selectively on inner sidewalls of the via and a trench formed in the dielectric layer, selectively filling the via with a first conductive material at least partially and simultaneously depositing the first conductive material on the barrier layer on the inner sidewalls of the via and the trench, to form a liner on the inner sidewalls of the via and the trench, and filling the remaining of the via and the trench with a second conductive material.