METHODS AND APPARATUS FOR INTERMIXING LAYER FOR ENHANCED METAL REFLOW

    公开(公告)号:US20220084882A1

    公开(公告)日:2022-03-17

    申请号:US17022058

    申请日:2020-09-15

    Abstract: Methods and apparatus for filling features on a substrate are provided herein. In some embodiments, a method of filling features on a substrate includes: depositing a first metallic material on the substrate and within a feature disposed in the substrate in a first process chamber via a chemical vapor deposition (CVD) process at a first temperature; depositing a second metallic material on the first metallic material in a second process chamber at a second temperature and at a first bias power to form a seed layer of the second metallic material; etching the seed layer in the second process chamber at a second bias power greater than the first bias power to form an intermix layer within the feature comprising the first metallic material and the second metallic material; and heating the substrate to a third temperature greater than the second temperature, causing a reflow of the second metallic material.

    METHODS TO FORM METAL LINERS FOR INTERCONNECTS

    公开(公告)号:US20240153816A1

    公开(公告)日:2024-05-09

    申请号:US17980850

    申请日:2022-11-04

    Abstract: A method for forming a metal liner layer for an interconnect uses a multi-metal deposition process to produce a reduced thickness liner. The back-end-of-the-line packaging process may include forming a metal liner layer by depositing a ruthenium layer with a first thickness of approximately 5 angstroms or less and depositing a first cobalt layer with a second thickness of approximately 20 angstroms or less. In some embodiments, the ruthenium layer may be deposited on a previously formed barrier layer and then undergoes a treatment process before depositing the first cobalt layer. In some embodiments, the first cobalt layer may be deposited on the ruthenium layer or the ruthenium layer maybe deposited on the first cobalt layer. In some embodiments, the ruthenium layer is deposited on the first cobalt layer and a second cobalt layer is deposited on the ruthenium layer.

    METHODS FOR EXTENDING CHAMBER COMPONENT LIFE FOR PLASMA PROCESSING SEMICONDUCTOR APPLICATIONS
    8.
    发明申请
    METHODS FOR EXTENDING CHAMBER COMPONENT LIFE FOR PLASMA PROCESSING SEMICONDUCTOR APPLICATIONS 审中-公开
    用于扩展等离子体处理半导体应用的室内组件寿命的方法

    公开(公告)号:US20150294843A1

    公开(公告)日:2015-10-15

    申请号:US14249042

    申请日:2014-04-09

    CPC classification number: H01J37/32862 H01J37/32853

    Abstract: Embodiments of the present invention generally provide chamber cleaning methods for cleaning a plasma processing chamber with minimum likelihood of erosion occurred on the chamber components so as to extend service life of chamber components for semiconductor plasma applications. In one embodiment, a method of extending chamber component life in a processing chamber includes supplying a cleaning gas mixture into a plasma processing chamber, applying a RF source power to the plasma processing chamber, and applying a voltage to a substrate support assembly disposed in the processing chamber during cleaning.

    Abstract translation: 本发明的实施例通常提供用于清洁等离子体处理室的室清洁方法,其中在室部件上发生最小的侵蚀可能性,以延长半导体等离子体应用的室部件的使用寿命。 在一个实施例中,一种在处理室中延长腔室部件寿命的方法包括将清洁气体混合物供应到等离子体处理室中,将RF源功率施加到等离子体处理室,以及向设置在等离子体处理室中的衬底支撑组件施加电压 处理室清洁。

    SELECTIVE COBALT DEPOSITION ON COPPER SURFACES

    公开(公告)号:US20210062330A1

    公开(公告)日:2021-03-04

    申请号:US17002296

    申请日:2020-08-25

    Abstract: A method for capping a copper surface on a substrate. In embodiments, the methods include exposing a substrate including a copper surface and a dielectric surface to a cobalt precursor gas and a process gas including a reducing agent to selectively form a first cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, wherein a flow rate ratio of process gas to cobalt precursor gas is at least 300:1.

    METAL IMPLANTATION TO BARRIER OR LINER FOR INTERCONNECT

    公开(公告)号:US20250062160A1

    公开(公告)日:2025-02-20

    申请号:US18749589

    申请日:2024-06-20

    Abstract: A method of forming a metal interconnect in a semiconductor structure includes performing a barrier layer deposition process to deposit a barrier layer within an opening formed through a dielectric layer, performing a liner deposition process to deposit a liner layer on the barrier layer, performing a metal treatment process to implant metal dopants into a surface of the liner layer, and performing a gap fill process to form a metal interconnect on the metal treated surface of the liner layer within the opening.

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