公开(公告)号：US20180184373A1

公开(公告)日：2018-06-28

申请号：US15389165

申请日：2016-12-22

Applicant: Applied Micro Circuits Corporation

Inventor： Francesco CAGGIONI ,  Dimitrios GIANNAKOPOULOS

IPC: H04W52/02 ,  H04W24/02 ,  H04W56/00

CPC classification number: H04W52/0212 ,  H04L1/0053 ,  H04L7/04 ,  H04W24/02 ,  H04W56/001 ,  Y02D70/00

Abstract: System and method of frame alignment at a receiver with power optimization mechanisms. A framer at the receiver is configured to process data streams from multiple physical lanes and/or multiple channels serially. The receiver may include multiple framers that process different sets of data streams in parallel. A framer may enter a power reduction mode after all the channels associated therewith have achieved frame alignment. The framer can be restarted to perform frame alignment processes on a particular channel responsive to an indication that the channel transitions to an out-of-frame state. The “out-of-frame” indication may be generated by a forward error correction (FEC) decoder when it detects an excessive number of uncorrectable errors in the channel.

公开(公告)号：US20180183565A1

公开(公告)日：2018-06-28

申请号：US15389179

申请日：2016-12-22

Applicant: Applied Micro Circuits Corporation

Inventor： Francesco CAGGIONI ,  Dimitrios GIANNAKOPOULOS

IPC: H04L7/00

CPC classification number: H04L7/0054 ,  H04J3/0608 ,  H04L1/00 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0079 ,  H04L7/048 ,  H04L12/12 ,  H04L12/40 ,  H04L25/14

Abstract: System and method of frame alignment at a receiver with power optimization mechanisms. A framer uses one or more comparators to search for the FAW in the incoming data, with each comparator configured to serially compare multiple windows of a parallel M-bit block (as provided from a parallel data bus) with the FAW. Multiple comparators in the framer may operate in parallel to search for the FAW at different windows. This configuration can significantly reduce the comparator count and so the gate count as well as the chip area in a framer. Power consumption can be advantageously reduced as one comparator operating serially consumes less power than multiple comparators in parallel because less gate toggling is involved.

公开(公告)号：US20180183564A1

公开(公告)日：2018-06-28

申请号：US15389140

申请日：2016-12-22

Applicant: Applied Micro Circuits Corporation

Inventor： Francesco CAGGIONI ,  Dimitrios GIANNAKOPOULOS

IPC: H04L7/00

CPC classification number: H04L7/0054 ,  H04L1/0047 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0079 ,  H04L7/04

Abstract: System and method of frame alignment at a receiver with power optimization mechanisms. A framer is configured to perform a frame alignment process on a data stream and enter an inactive state after frame alignment is achieved. In the inactive state, the circuits used to perform the frame alignment process in the framer can be powered down or otherwise placed in a power reduction mode. Responsive to an indication that data processing at the receiver becomes “out-of-frame” again, the framer can wake up from the inactive state and restart the frame alignment process. An “out-of-frame” indication may be generated by error detection logic (e.g., forward error correction (FEC) decoder) when it detects an excessive number of uncorrectable errors.