公开(公告)号：US20200012822A1

公开(公告)日：2020-01-09

申请号：US16030459

申请日：2018-07-09

Applicant: Arm Limited

Inventor： Carl Wayne VINEYARD ,  Christopher Neal HINDS ,  Adeline-Fleur FLEMING

IPC: G06F21/77 ,  G06F21/72 ,  G06F21/56

Abstract: A computing device incorporating repetitive side channel attack (SCA) countermeasures can include a timer circuit and a capacitive delay circuit that notifies of a potential repetitive-based attack by sending an activity-detected signal that can be used to initiate an appropriate countermeasure response. Additionally, or independently, a computing device incorporating repetitive SCA countermeasures can include at least one storage unit that can store an incoming input signal, at least one comparator to compare the incoming input signal with another signal and indicate a match, and a counter that increments upon the match. When the counter reaches a specified limit, a limit-exceeded signal can be sent to notify of a potential repetitive-based attack and initiate an appropriate countermeasure response.

公开(公告)号：US20180336372A1

公开(公告)日：2018-11-22

申请号：US15967900

申请日：2018-05-01

Applicant: Arm Limited

Inventor： Adeline-Fleur FLEMING ,  Carl Wayne VINEYARD ,  George McNeil LATTIMORE ,  Christopher Neal HINDS ,  Robert John HARRISON ,  Mikael RIEN ,  Abdellah BAKHALI ,  Robert Christiaan SCHOUTEN ,  Jean-Charles BOLINHAS

IPC: G06F21/75 ,  H02J7/00 ,  H03K5/24

CPC classification number: H02J7/0068 ,  H01L27/00 ,  H02J7/0054 ,  H02J7/345

Abstract: Power is received from a first power signal at a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply.

公开(公告)号：US20180337767A1

公开(公告)日：2018-11-22

申请号：US15600974

申请日：2017-05-22

Applicant: ARM Limited

Inventor： Robert John HARRISON ,  Mikael RIEN ,  Carl Wayne VINEYARD ,  George McNeil LATTIMORE ,  Christopher Neal HINDS ,  Adeline-Fleur FLEMING

IPC: H04L9/00 ,  G06F1/26 ,  G06F1/04 ,  G06F21/60

Abstract: Power is received from a first power signal a first of a plurality of charge stores. A second power signal is output from a second of the plurality of charge stores. The second power signal is isolated from the first power supply.