公开(公告)号：US11153231B2

公开(公告)日：2021-10-19

申请号：US16516698

申请日：2019-07-19

Applicant: Arm Limited

Inventor： Tessil Thomas ,  Andrew Joseph Rushing

IPC: H04L12/861 ,  H04L12/741 ,  G06F12/0804 ,  G06F3/06

Abstract: An apparatus and method are provided for processing flush requests within a packet network. The apparatus comprises a requester device within the packet network arranged to receive a flush request generated by a remote agent requesting that one or more data items be flushed to a point of persistence. The requester device translates the flush request into a packet-based flush command conforming to a packet protocol of the packet network. A completer device within the packet network that is coupled to a persistence domain incorporating the point of persistence is arranged to detect receipt of the packet-based flush command, and then trigger a flush operation within the persistence domain to flush the one or more data items to the point of persistence. This provides a fast, hardware-based, mechanism for performing a flush operation within a persistence domain without needing to trigger software in the persistence domain to handle the flush to the point of persistence.

公开(公告)号：US10915404B2

公开(公告)日：2021-02-09

申请号：US16178681

申请日：2018-11-02

Applicant: Arm Limited

Inventor： Andrew Joseph Rushing

IPC: G06F11/14 ,  G06F1/30 ,  G06F11/07 ,  G06F12/0811 ,  G06F12/1027

Abstract: A data processing apparatus is provided that comprises volatile storage circuitry to store data while power is provided. Persistent storage circuitry stores data in the absence of power and transfer circuitry transfers data from the volatile storage circuitry to the persistent storage circuitry. The transfer circuitry is adapted to transfer the data from the volatile storage circuitry to the persistent storage circuitry in response to a primary power supply becoming unavailable to the volatile storage circuitry. The transfer circuitry is adapted to transfer a subset of the data from the volatile storage circuitry to the persistent storage circuitry in response to an explicit request comprising an indication of the subset of the data.

公开(公告)号：US09996471B2

公开(公告)日：2018-06-12

申请号：US15194902

申请日：2016-06-28

Applicant: ARM Limited

Inventor： Ali Saidi ,  Kshitij Sudan ,  Andrew Joseph Rushing ,  Andreas Hansson ,  Michael Filippo

IPC: G06F12/0871 ,  G06F12/0873 ,  G06F12/0895

CPC classification number: G06F12/0871 ,  G06F12/0868 ,  G06F12/0873 ,  G06F12/0895 ,  G06F2212/305 ,  G06F2212/401 ,  G06F2212/466

Abstract: Cache line data and metadata are compressed and stored in first and, optionally, second memory regions, the metadata including an address tag When the compressed data fit entirely within a primary block in the first memory region, both data and metadata are retrieved in a single memory access. Otherwise, overflow data is stored in an overflow block in the second memory region. The first and second memory regions may be located in the same row of a DRAM, for example, or in different regions of a DRAM and may be configured to enable standard DRAM components to be used. Compression and decompression logic circuits may be included in a memory controller.