公开(公告)号：US20220405597A1

公开(公告)日：2022-12-22

申请号：US17349780

申请日：2021-06-16

Applicant: Arm Limited

Inventor： Urmish Ajit Thakker ,  Jesse Garrett Beu ,  Dibakar Gope ,  Mark John O'Connor

IPC: G06N3/08 ,  G06N3/04 ,  G06K9/62 ,  G06K9/46 ,  G06K9/00 ,  G10L15/02 ,  G10L15/16

Abstract: Example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to adapt a computing device to classify physical features in a deployment environment. In a particular implementation, computing resources may be selectively de-allocated from at least one of one or more elements of a computing architecture based, at least in part, on assessed impacts to the one or more elements of the computing architecture.

公开(公告)号：US20210089888A1

公开(公告)日：2021-03-25

申请号：US16836110

申请日：2020-03-31

Applicant: Arm Limited

Inventor： Dibakar Gope ,  Jesse Garrett Beu ,  Paul Nicholas Whatmough ,  Matthew Mattina

IPC: G06N3/08 ,  G06F7/483

Abstract: The present disclosure advantageously provides a system including a memory, a processor, and a circuitry to execute one or more mixed precision layers of an artificial neural network (ANN), each mixed precision layer including high-precision weight filters and low precision weight filters. The circuitry is configured to perform one or more calculations on an input feature map having a plurality of input channels (cin) using the high precision weight filters to create a high precision output feature map having a first number of output channels (k), perform one or more calculations on the input feature map using the low precision weight filters to create a low precision output feature map having a second number of output channels (cout−k), and concatenate the high precision output feature map and the low precision output feature map to create a unified output feature map having a plurality of output channels (cout).

公开(公告)号：US20250028933A1

公开(公告)日：2025-01-23

申请号：US18356091

申请日：2023-07-20

Applicant: Arm Limited

Inventor： Gerti Tuzi ,  Dibakar Gope

IPC: G06N3/045 ,  G06N3/08

Abstract: Example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to estimate an execution latency of a candidate neural network in a neural network architecture search (NAS) process.

公开(公告)号：US20230195419A1

公开(公告)日：2023-06-22

申请号：US17554024

申请日：2021-12-17

Applicant: Arm Limited

Inventor： Dibakar Gope ,  Jesse Garrett Beu ,  Milos Milosavljevic

IPC: G06F7/544 ,  G06N3/04

CPC classification number: G06F7/5443 ,  G06N3/04 ,  G06F2207/4824

Abstract: A neural network system, method and apparatus are provided. A truth table matrix, an index vector and an input data tensor are read from a memory. At least a portion of the input data tensor is flattened into an input data vector. A scatter accumulate instruction is executed on the index vector and the input data vector to generate an intermediate vector. The truth table matrix and the intermediate vector are then multiplied to generate an output data vector.

公开(公告)号：US12067373B2

公开(公告)日：2024-08-20

申请号：US16836110

申请日：2020-03-31

Applicant: Arm Limited

Inventor： Dibakar Gope ,  Jesse Garrett Beu ,  Paul Nicholas Whatmough ,  Matthew Mattina

IPC: G06F7/483 ,  G06F7/544 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

CPC classification number: G06F7/483 ,  G06F7/5443 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: The present disclosure advantageously provides a system including a memory, a processor, and a circuitry to execute one or more mixed precision layers of an artificial neural network (ANN), each mixed precision layer including high-precision weight filters and low precision weight filters. The circuitry is configured to perform one or more calculations on an input feature map having a plurality of input channels (cin) using the high precision weight filters to create a high precision output feature map having a first number of output channels (k), perform one or more calculations on the input feature map using the low precision weight filters to create a low precision output feature map having a second number of output channels (cout−k), and concatenate the high precision output feature map and the low precision output feature map to create a unified output feature map having a plurality of output channels (cout).

公开(公告)号：US11561767B2

公开(公告)日：2023-01-24

申请号：US16836117

申请日：2020-03-31

Applicant: Arm Limited

Inventor： Dibakar Gope ,  Jesse Garrett Beu ,  Paul Nicholas Whatmough ,  Matthew Mattina

IPC: G06F7/483 ,  G06N3/063 ,  G06N3/08 ,  G06F7/544 ,  G06N3/04

Abstract: The present disclosure advantageously provides a mixed precision computation (MPC) unit for executing one or more mixed-precision layers of an artificial neural network (ANN). The MPC unit includes a multiplier circuit configured to input a pair of operands and output a product, a first adder circuit coupled to the multiplier circuit, a second adder circuit, coupled to the first adder circuit, configured to input a pair of operands, an accumulator circuit, coupled to the multiplier circuit and the first adder circuit, configured to output an accumulated value, and a controller, coupled to the multiplier circuit, the first adder circuit, the second adder circuit and the accumulator circuit, configured to input a mode control signal. The controller has a plurality of operating modes including a high precision mode, a low precision add mode and a low precision multiply mode.

公开(公告)号：US20210089889A1

公开(公告)日：2021-03-25

申请号：US16836117

申请日：2020-03-31

Applicant: Arm Limited

Inventor： Dibakar Gope ,  Jesse Garrett Beu ,  Paul Nicholas Whatmough ,  Matthew Mattina

IPC: G06N3/08

Abstract: The present disclosure advantageously provides a mixed precision computation (MPC) unit for executing one or more mixed-precision layers of an artificial neural network (ANN). The MPC unit includes a multiplier circuit configured to input a pair of operands and output a product, a first adder circuit coupled to the multiplier circuit, a second adder circuit, coupled to the first adder circuit, configured to input a pair of operands, an accumulator circuit, coupled to the multiplier circuit and the first adder circuit, configured to output an accumulated value, and a controller, coupled to the multiplier circuit, the first adder circuit, the second adder circuit and the accumulator circuit, configured to input a mode control signal. The controller has a plurality of operating modes including a high precision mode, a low precision add mode and a low precision multiply mode.