公开(公告)号：US20230289576A1

公开(公告)日：2023-09-14

申请号：US17689755

申请日：2022-03-08

申请人： Arm Limited

发明人： Fernando García Redondo ,  Mudit Bhargava ,  Paul Nicholas Whatmough ,  Shidhartha Das

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/08

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/082

摘要： Various implementations described herein are directed to a device having neural network circuitry with an array of synapse cells arranged in columns and rows. The device may have input circuitry that provides voltage to the synapse cells by way of row input lines for the rows in the array. The device may have output circuitry that receives current from the synapse cells by way of column output lines for the columns in the array. Also, conductance for the synapse cells in the array may be determined based on the voltage provided by the input circuitry and the current received by the output circuitry.

公开(公告)号：US12080378B2

公开(公告)日：2024-09-03

申请号：US17709076

申请日：2022-03-30

申请人： Arm Limited

发明人： Fernando García Redondo ,  Pranay Prabhat ,  Mudit Bhargava ,  Supreet Jeloka

IPC分类号： G11C7/12 ,  G11C5/12 ,  G11C7/16 ,  G11C7/18 ,  G11C8/08

CPC分类号： G11C7/12 ,  G11C5/12 ,  G11C7/16 ,  G11C7/18 ,  G11C8/08

摘要： According to one implementation of the present disclosure, a circuit comprises: a memory array comprising one or more groupings of bitcells, one or more bitlines, and one or more wordlines; and one or more canary circuits coupled to the memory array, wherein each of the canary circuits is configured to predict at least partial breakdown of a corresponding grouping of bitcells in the memory array. According to one implementation of the present disclosure, a method includes: providing an excitation stress on one or more canary circuits corresponding to a grouping of bitcells in a memory array; detecting at least a partial breakdown of the one or more canary circuits; and generating a flag.

公开(公告)号：US20230317126A1

公开(公告)日：2023-10-05

申请号：US17709076

申请日：2022-03-30

申请人： Arm Limited

发明人： Fernando García Redondo ,  Pranay Prabhat ,  Mudit Bhargava ,  Supreet Jeloka

IPC分类号： G11C7/12 ,  G11C7/18 ,  G11C7/16 ,  G11C8/08 ,  G11C5/12

CPC分类号： G11C7/12 ,  G11C7/18 ,  G11C7/16 ,  G11C8/08 ,  G11C5/12

摘要： According to one implementation of the present disclosure, a circuit comprises: a memory array comprising one or more groupings of bitcells, one or more bitlines, and one or more wordlines; and one or more canary circuits coupled to the memory array, wherein each of the canary circuits is configured to predict at least partial breakdown of a corresponding grouping of bitcells in the memory array. According to one implementation of the present disclosure, a method includes: providing an excitation stress on one or more canary circuits corresponding to a grouping of bitcells in a memory array; detecting at least a partial breakdown of the one or more canary circuits; and generating a flag.