-
公开(公告)号：US09779536B2
公开(公告)日：2017-10-03
申请号：US14790452
申请日：2015-07-02
Applicant: ARM Limited
Inventor： Andreas Engh-Halstvedt , Daren Croxford , Frank Langtind
CPC classification number: G06T15/005
Abstract: A graphics processing pipeline (20) comprises first vertex shading circuitry (21) that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline. Tiling circuitry (22) then determines for the vertices that have been subjected to the first vertex shading operation, whether the vertices should be processed further. A second vertex shading circuitry (23) then performs a second vertex shading operation on the vertices that it has been determined should be processed further, to vertex shade the remaining vertex attributes for each vertex that it has been determined should be processed further.
-
公开(公告)号：US20170061678A1
公开(公告)日：2017-03-02
申请号：US15246970
申请日：2016-08-25
Applicant: ARM Limited
Inventor： Andreas Due Engh-Halstvedt , Frank Langtind
CPC classification number: G06T15/40 , G06T15/005
Abstract: A tile-based graphics processing pipeline includes a back-facing determination and culling unit that is operable to cull back-facing triangles before the tiling stage. The back-facing determination and culling unit include a triangle size estimator that estimates the size of a triangle being considered. If the size of the triangle is less than a selected size, then the area of the triangle is calculated using fixed point arithmetic and the result of that area calculation is used by a back-face culling unit to determine whether to cull the triangle or not. On the other hand, if the size estimator determines that the primitive is greater than the selected size, then the triangle bypasses the fixed point area calculation and back-face culling unit and is instead passed directly to the tiler.
Abstract translation: 基于瓦片的图形处理流水线包括背面确定和剔除单元，其可操作以在平铺阶段之前拣出背面三角形。 背面确定和剔除单元包括估计所考虑的三角形的尺寸的三角形尺寸估计器。 如果三角形的尺寸小于所选择的尺寸，则使用定点运算来计算三角形的面积，并且该面积计算的结果由背面拣选单元使用以确定是否剔除三角形 。 另一方面，如果尺寸估计器确定原始尺寸大于所选择的尺寸，则三角形绕过固定点区域计算和背面拣选单元，而是直接传递给平铺机。
-
公开(公告)号：US20160005140A1
公开(公告)日：2016-01-07
申请号：US14790452
申请日：2015-07-02
Applicant: ARM Limited
Inventor： Andreas Engh-Halstvedt , Daren Croxford , Frank Langtind
IPC: G06T1/20
CPC classification number: G06T15/005
Abstract: A graphics processing pipeline (20) comprises first vertex shading circuitry (21) that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline. Tiling circuitry (22) then determines for the vertices that have been subjected to the first vertex shading operation, whether the vertices should be processed further. A second vertex shading circuitry (23) then performs a second vertex shading operation on the vertices that it has been determined should be processed further, to vertex shade the remaining vertex attributes for each vertex that it has been determined should be processed further.
Abstract translation: 图形处理流水线（20）包括第一顶点着色电路（21），其操作以由图形处理流水线处理的一组顶点的顶点的顶点颜色位置属性。 平铺电路（22）然后确定已经经受第一顶点着色操作的顶点，是否应进一步处理顶点。 然后，第二顶点着色电路（23）对顶点执行第二顶点着色操作，以确定应进一步处理顶点着色操作，以便顶点遮蔽其应确定的每个顶点的剩余顶点属性应进一步处理。
-
Patent Agency Ranking
公开(公告)号：US10650577B2
公开(公告)日：2020-05-12
申请号：US15246970
申请日：2016-08-25
Applicant: ARM Limited
Inventor： Andreas Due Engh-Halstvedt , Frank Langtind
Abstract: A tile-based graphics processing pipeline includes a back-facing determination and culling unit that is operable to cull back-facing triangles before the tiling stage. The back-facing determination and culling unit include a triangle size estimator that estimates the size of a triangle being considered. If the size of the triangle is less than a selected size, then the area of the triangle is calculated using fixed point arithmetic and the result of that area calculation is used by a back-face culling unit to determine whether to cull the triangle or not. On the other hand, if the size estimator determines that the primitive is greater than the selected size, then the triangle bypasses the fixed point area calculation and back-face culling unit and is instead passed directly to the tiler.
-
公开(公告)号：US10599584B2
公开(公告)日：2020-03-24
申请号：US15806237
申请日：2017-11-07
Applicant: Arm Limited
Inventor： Andreas Due Engh-Halstvedt , Frank Langtind , Shareef Justin Jalloq
IPC: G06F12/10 , G06F12/1045 , G06F12/0804 , G06F12/0891 , G06F12/0875 , G06F12/126 , G06F12/0895
Abstract: When writing data to memory via a write buffer including a write cache containing a plurality of lines for storing data to be written to memory and an address-translation cache that stores a list of virtual address to physical address translations, a record of a set of lines of the write cache that are available to be evicted to the memory is maintained, and the evictable lines in the record of evictable lines are processed by requesting from the address-translation cache a respective physical address for each virtual address associated with an evictable line. The address-translation cache returns a hit or a miss status to the write buffer for each evictable line that is checked, and the write buffer writes out to memory at least one of the evictable lines for which a hit status was returned.
-
公开(公告)号：US20170193691A1
公开(公告)日：2017-07-06
申请号：US15393120
申请日：2016-12-28
Applicant: ARM Limited
Inventor： Frank Langtind , Andreas Due Engh-Halstvedt , Sandeep Kakarlapudi
CPC classification number: G06T15/80 , G06F9/3879 , G06T1/20 , G06T15/005 , G06T17/20 , G09G5/363
Abstract: A graphics processing pipeline includes position shading circuitry, a tiler, varying-only vertex shading circuitry and fragment (frontend) shading circuitry. The tiler reads a list of indices defining a set of vertices to be processed by the graphics processing pipeline and determines whether or not vertex shading is required for the positional attributes of the vertices. If vertex shading is required, the tiler sends a position shading request for the vertices to the position shading circuitry. The tiler uses the vertex shaded position data to identify primitives that should be processed further to generate the render output and that accordingly should be subjected to a second, varying shading, vertex shading operation. When the tiler determines that a vertex (or group of vertices) should be subjected to the second, varying shading, vertex shading operation, the tiler sends a varying shading request for the vertex (or vertices) to the varying shading circuitry.
-
公开(公告)号：US20190138458A1
公开(公告)日：2019-05-09
申请号：US15806237
申请日：2017-11-07
Applicant: Arm Limited
Inventor： Andreas Due Engh-Halstvedt , Frank Langtind , Shareef Justin Jalloq
IPC: G06F12/1045 , G06F12/0804 , G06F12/0875 , G06F12/0891
CPC classification number: G06F12/1045 , G06F12/0804 , G06F12/0875 , G06F12/0891 , G06F12/0895 , G06F12/126 , G06F2212/50 , G06F2212/683
Abstract: When writing data to memory via a write buffer including a write cache containing a plurality of lines for storing data to be written to memory and an address-translation cache that stores a list of virtual address to physical address translations, a record of a set of lines of the write cache that are available to be evicted to the memory is maintained, and the evictable lines in the record of evictable lines are processed by requesting from the address-translation cache a respective physical address for each virtual address associated with an evictable line. The address-translation cache returns a hit or a miss status to the write buffer for each evictable line that is checked, and the write buffer writes out to memory at least one of the evictable lines for which a hit status was returned.
-
公开(公告)号：US10255718B2
公开(公告)日：2019-04-09
申请号：US15393120
申请日：2016-12-28
Applicant: ARM Limited
Inventor： Frank Langtind , Andreas Due Engh-Halstvedt , Sandeep Kakarlapudi
Abstract: A graphics processing pipeline includes position shading circuitry, a tiler, varying-only vertex shading circuitry and fragment (frontend) shading circuitry. The tiler reads a list of indices defining a set of vertices to be processed by the graphics processing pipeline and determines whether or not vertex shading is required for the positional attributes of the vertices. If vertex shading is required, the tiler sends a position shading request for the vertices to the position shading circuitry. The tiler uses the vertex shaded position data to identify primitives that should be processed further to generate the render output and that accordingly should be subjected to a second, varying shading, vertex shading operation. When the tiler determines that a vertex (or group of vertices) should be subjected to the second, varying shading, vertex shading operation, the tiler sends a varying shading request for the vertex (or vertices) to the varying shading circuitry.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.013 seconds)
