公开(公告)号：US20240086202A1

公开(公告)日：2024-03-14

申请号：US17942554

申请日：2022-09-12

Applicant: Arm Limited

Inventor： Matthew James WALKER ,  Mbou EYOLE ,  Giacomo GABRIELLI ,  Balaji VENU ,  Wei WANG

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F9/3855 ,  G06F9/30145 ,  G06F9/32

Abstract: An apparatus, method and computer program, the apparatus comprising processing circuitry to execute instructions, issue circuitry to issue the instructions for execution by the processing circuitry, and candidate instruction storage circuitry to store a plurality of condition-dependent instructions, each specifying at least one condition. The issue circuitry is configured to issue a given condition-dependent instruction in response to a determination or a prediction of the at least one condition specified by the given condition-dependent instruction being met, and when the given condition-dependent instruction is a sequence-start instruction, the issue circuitry is responsive to the determination or prediction to issue a sequence of instructions comprising the sequence-start instruction and at least one subsequent instruction.

公开(公告)号：US20240086196A1

公开(公告)日：2024-03-14

申请号：US17941387

申请日：2022-09-09

Applicant: Arm Limited

Inventor： Matthew James WALKER ,  Mbou EYOLE ,  Giacomo GABRIELLI ,  Balaji VENU

IPC: G06F9/30 ,  G06F9/48

CPC classification number: G06F9/30123 ,  G06F9/4881

Abstract: There is provided an apparatus, method and medium for data processing. The apparatus comprises a register file comprising a plurality of data registers, and frontend circuitry responsive to an issued instruction, to control processing circuitry to perform a processing operation to process an input data item to generate an output data item. The processing circuitry is responsive to a first encoding of the issued instruction specifying a data register, to read the input data item from the data register, and/or write the output data item to the data register. The processing circuitry is responsive to a second encoding of the issued instruction specifying a buffer-region of the register file for storing a queue of data items, to perform the processing operation and to perform a dequeue operation to dequeue the input data item from the queue, and/or perform an enqueue operation to enqueue the output data item to the queue.

公开(公告)号：US20240086201A1

公开(公告)日：2024-03-14

申请号：US17941404

申请日：2022-09-09

Applicant: Arm Limited

Inventor： Matthew James WALKER ,  Mbou EYOLE ,  Giacomo GABRIELLI ,  Balaji VENU

IPC: G06F9/38

CPC classification number: G06F9/3855 ,  G06F9/3802

Abstract: One or more triggered-instruction processing elements are provided, a given triggered-instruction processing element comprising execution circuitry to execute processing operations in response to instructions according to a triggered instruction architecture. Input channel processing circuitry receives a given tagged data item (comprising a data value and a tag value) for a given input channel, and in response controls enqueuing of the data value of the given tagged data item to a selected buffer structure selected from among at least two buffer structures mapped onto register storage accessible to one or more of the triggered-instruction processing elements in response to a computation instruction for controlling performance of a computation operation. The selected buffer structure is selected based at least on the tag value, so data values of tagged data items specifying different tag values for the given input channel are allocatable to different buffer structures.

公开(公告)号：US20230046064A1

公开(公告)日：2023-02-16

申请号：US17760190

申请日：2021-02-08

Applicant: ARM LIMITED ,  UNIVERSITY OF SOUTHAMPTON

Inventor： Parameshwarappa Anand Kumar SAVANTH ,  Alexander Stewart WEDDELL ,  Matthew James WALKER ,  Wei WANG ,  James Edward MYERS

IPC: G06F1/3228 ,  G06F1/3296

Abstract: A computer-implemented method comprises generating computer executable code as one or more code portions; detecting a number of processing operations required to reach one or more predetermined stages in execution of each code portion; and associating with each code portion one or more progress indicators, each representing a respective execution stage of the one or more predetermined stages within execution of that code portion. The code portions are executed by a processor powered by an unpredictable power source. When the processor detects an energy condition indicating that no more than a reserve quantity of electrical energy is available, the progress indicators are used to determine whether or not to perform a checkpoint.