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    Clock Phase-Shifting Techniques
    3.
    发明申请
    Clock Phase-Shifting Techniques 有权

    公开(公告)号：US20220166436A1

    公开(公告)日：2022-05-26

    申请号：US17103585

    申请日：2020-11-24

    Applicant: Arm Limited

    Inventor： Benoit Labbe ,  Shidhartha Das ,  Thanusree Achuthan

    IPC: H03L7/081 ,  H03L7/085 ,  G06F1/10 ,  G06F1/324

    Abstract: Various implementations described herein are related to a device. The device may include first circuitry that receives a clock signal and provides one or more phase-shifted pulse signals based on the clock signal. The device may include second circuitry that receives an input voltage, receives the clock signal, and provides an internal control signal based on the input voltage and the clock signal. The device may include third circuitry that receives the internal control signal, receives the one or more phase-shifted pulse signals, and provides an output clock signal based on the internal control signal and the one or more phase-shifted pulse signals.

    Circuits and methods for set and reset signals
    4.
    发明授权
    Circuits and methods for set and reset signals 有权

    公开(公告)号：US12047083B2

    公开(公告)日：2024-07-23

    申请号：US17519490

    申请日：2021-11-04

    Applicant: Arm Limited

    Inventor： El Mehdi Boujamaa ,  Benoit Labbe ,  David Michael Bull

    IPC: H03L7/091 ,  G06F1/08 ,  G06F1/12 ,  H03L7/081

    CPC classification number: H03L7/091 ,  G06F1/08 ,  G06F1/12 ,  H03L7/0814

    Abstract: In one particular implementation, a circuit includes: a flip flop; and an AND gate, where the circuit is configured to generate edge-triggered set and reset input signals. In another implementation, a method includes: providing, by a digital locked loop (DLL), a plurality of phase outputs; determining, by respective logic circuits, respective pulses to be selected for an output clock corresponding to each of the plurality phase outputs; shifting respective selection windows of the pulses such that each of the selection windows fully overlap the corresponding respective determined pulses; and selecting the pulses.

    Observer Based Voltage Regulation Circuitry
    8.
    发明公开
    Observer Based Voltage Regulation Circuitry 审中-公开

    公开(公告)号：US20230291311A1

    公开(公告)日：2023-09-14

    申请号：US17690343

    申请日：2022-03-09

    Applicant: Arm Limited

    Inventor： Benoit Labbe ,  Shidhartha Das ,  Chi-Hsiang Huang

    IPC: H02M3/157 ,  H02M3/158

    CPC classification number: H02M3/157 ,  H02M3/158

    Abstract: Various implementations described herein are related to a device having a power stage that provides an output signal and a first feedback signal based on an input signal and a control signal. The device may have a digital stage with digital circuitry that provides a second feedback signal based on operational activity of the digital circuitry using the output signal. The device may have a control stage that provides the control signal based on the input signal, the first feedback signal and the second feedback signal.

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