公开(公告)号：US09886276B2

公开(公告)日：2018-02-06

申请号：US14511388

申请日：2014-10-10

Applicant: ARM LIMITED

Inventor： Loïc Pierron ,  Antony John Penton

IPC: G06F9/30 ,  G06F9/40

CPC classification number: G06F9/30145 ,  G06F9/30123

Abstract: A data processing apparatus for accessing several system registers using a single command includes system registers and command generation circuitry capable of analysing a plurality of decoded system register access instructions, each specifying a system register identifier. In response to a predetermined condition, the command generation circuitry generates a single command to represent the plurality of decoded system register access instructions. The predetermined condition comprises a requirement that a total width of the system registers specified by the plurality of decoded system register access instructions is less than or equal to a predefined data processing width.

公开(公告)号：US10910082B1

公开(公告)日：2021-02-02

申请号：US16527228

申请日：2019-07-31

Applicant: Arm Limited

Inventor： Alan Jeremy Becker ,  Loïc Pierron

IPC: G11C29/38 ,  G11C29/18 ,  G11C11/417 ,  G11C11/419 ,  G11C11/418

Abstract: Apparatus comprises memory circuitry having a plurality of addressable memory entries storing respective data items and associated error protection codes; memory error protection circuitry to generate the error protection code for a data item stored to the memory circuitry, the error protection code for a given data item stored to the memory circuitry depending upon at least the given data item and a memory address defining a memory entry to which the given data item is stored, and to perform a check operation to check for consistency between a retrieved data item, the memory address defining a memory entry from which the given data item is retrieved and the error protection code associated with the retrieved data item; memory built-in self-test circuitry to test the memory and memory error protection circuitry; and access circuitry to provide an indirect access path between the memory built-in self-test circuitry a memory which accesses the memory circuitry via the memory error protection circuitry and a direct access path between the memory built-in self-test circuitry and a memory entry which bypasses the memory error protection circuitry; the memory built-in self-test circuitry being configured to execute a test operation by writing a test value to a first memory entry of the memory circuitry having a first test memory address via the indirect access path; retrieving the test value and associated error protection code from the first memory entry by the direct access path; writing the retrieved test value and associated error protection code to a second memory entry having a second test memory address via the direct access path, there being a difference in at least one bit between the first test memory address and the second test memory address; and retrieving the test value and associated error protection code from the second memory entry via the indirect access path; the memory built-in self-test circuitry comprising fault detection circuitry configured to detect a fault condition when the result of the check operation performed by the memory error protection circuitry is inconsistent with the difference between the first test memory address and the second test memory address.

公开(公告)号：US11221899B2

公开(公告)日：2022-01-11

申请号：US16580045

申请日：2019-09-24

Applicant: Arm Limited

Inventor： Kauser Yakub Johar ,  Loïc Pierron

IPC: G06F9/38 ,  G06F11/07 ,  G06F13/40 ,  G06F9/52 ,  G06F13/16 ,  G06F11/16

Abstract: An apparatus is described comprising a cluster of processing elements. The cluster having a split mode in which the processing elements are configured to process independent processing workloads, and a lock mode in which the processing elements comprise at least one primary processing element and at least one redundant processing element, each redundant processing element configured to perform a redundant processing workload for checking correctness of a primary processing workload performed by the primary processing element. Each processing element has an associated local memory comprising a plurality of memory locations. A local memory access control mechanism is configured, during the lock mode, to allow the at least one primary processing element to access memory locations within the local memory associated with the at least one redundant processing element.

公开(公告)号：US09880898B2

公开(公告)日：2018-01-30

申请号：US14793914

申请日：2015-07-08

Applicant: ARM LIMITED

Inventor： Michael Williams ,  Simon John Craske ,  Loïc Pierron

IPC: H04L1/18 ,  G06F11/10 ,  H04L1/00

CPC classification number: G06F11/1004 ,  H04L1/004 ,  H04L1/0045 ,  H04L1/0061 ,  H04L2001/0094

Abstract: Transmission control checking circuitry adds control check data to a transaction response which is received at a transaction master and compared with expected data at the transaction master. The expected data having control check data may be a unique transaction identifier. The transaction master generated the unique transaction identifier when it generated the transaction request and will check that the transaction responses include that unique transaction identifier. In this way, errors in the control of transmission of transactions (e.g., misrouting) may be detected.