公开(公告)号：US20230042247A1

公开(公告)日：2023-02-09

申请号：US17396865

申请日：2021-08-09

Applicant: Arm Limited

Inventor： Frederic Claude Marie PIRY ,  Cédric Denis Robert AIRAUD ,  Natalya BONDARENKO ,  Luca MARONCELLI ,  Geoffray Matthieu LACOURBA

IPC: G06F9/38 ,  G06F9/48 ,  G06F9/30

Abstract: A data processing apparatus comprises receiver circuitry for receiving instructions from each of a plurality of requester devices. Processing circuitry executes the instructions associated with each of a subset of the requester devices at a time and arbitration circuitry determines the subset of the requester devices and causes the instructions associated with each of the subset of the requester devices to be executed next. In response to the receiver circuitry receiving an instruction of a predetermined type from one of the requester devices outside the subset of requester devices, the arbitration circuitry causes the instruction of the predetermined type to be executed next.

公开(公告)号：US20240028516A1

公开(公告)日：2024-01-25

申请号：US18147068

申请日：2022-12-28

Applicant: Arm Limited

Inventor： Luca MARONCELLI ,  Cedric Denis Robert AIRAUD ,  Florent BEGON ,  Peter Raphael EID

IPC: G06F12/0862 ,  G06F12/0875

CPC classification number: G06F12/0862 ,  G06F12/0875 ,  G06F2212/6022

Abstract: A data processing apparatus is provided. Prefetch circuitry generates a prefetch request for a cache line prior to the cache line being explicitly requested. The cache line is predicted to be required for a store operation in the future. Issuing circuitry issues the prefetch request to a memory hierarchy and filter circuitry filters the prefetch request based on at least one other prefetch request made to the cache line, to control whether the prefetch request is issued by the issuing circuitry.

公开(公告)号：US20230342154A1

公开(公告)日：2023-10-26

申请号：US17724600

申请日：2022-04-20

Applicant: Arm Limited

Inventor： Luca MARONCELLI ,  Harvin IRIAWAN ,  Peter Raphael EID ,  Cédric Denis Robert AIRAUD

IPC: G06F9/38

CPC classification number: G06F9/3802 ,  G06F9/3851

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry, prefetch circuitry and prefetch metadata storage comprising a plurality of entries. Metadata items, each associated with a given stream of instructions, are stored in the prefetch metadata storage. Responsive to a given entry of the plurality of entries being associated with the given stream associated with a given metadata item, the given entry is updated. Responsive to no entry of the plurality of entries being associated with the given stream associated with a given metadata item, an entry is selected according to a default replacement policy, the given stream is allocated thereto, and the selected entry is updated based on the given metadata item. Responsive to a switch condition being met, the default selection policy is switched to an alternative selection policy comprising locking one or more entries by preventing allocation of streams to the locked entries.