公开(公告)号：US20240004611A1

公开(公告)日：2024-01-04

申请号：US17855856

申请日：2022-07-01

Applicant: Arm Limited

Inventor： Michael Alexander KENNEDY ,  Marco MONTAGNA ,  Karel Hubertus Gerardus WALTERS ,  Ian Michael CAULFIELD

IPC: G06F7/483

CPC classification number: G06F7/483

Abstract: Processing circuitry performs a processing operation to generate a two's complement result value representing a positive or negative number in two's complement representation. Normalization-and-rounding circuitry converts the two's complement result value to a normalized-and-rounded floating-point result value represented using sign-magnitude representation. The normalization-and-rounding circuitry comprises incrementing circuitry to perform an increment addition (e.g. a rounding increment or a conversion increment) to generate a fraction of the normalized-and-rounded floating-point result value. For an operation where the increment addition is required to be performed, tininess detection circuitry detects the after-rounding tininess status based on a still-to-be-incremented version of the normalized-and-rounded floating-point result value prior to the increment addition by the increment circuitry.