公开(公告)号：US20200257531A1

公开(公告)日：2020-08-13

申请号：US16864223

申请日：2020-05-01

Applicant: ARM Limited

Inventor： Peter Richard GREENHALGH ,  Simon John CRASKE ,  Ian Michael CAULFIELD ,  Max John BATLEY ,  Allan John SKILLMAN ,  Antony John PENTON

IPC: G06F9/30 ,  G06F9/38

Abstract: A processing pipeline may have first and second execution circuits having different performance or energy consumption characteristics. Instruction supply circuitry may support different instruction supply schemes with different energy consumption or performance characteristics. This can allow a further trade-off between performance and energy efficiency. Architectural state storage can be shared between the execute units to reduce the overhead of switching between the units. In a parallel execution mode, groups of instructions can be executed on both execute units in parallel.

公开(公告)号：US20190057093A1

公开(公告)日：2019-02-21

申请号：US15678464

申请日：2017-08-16

Applicant: ARM LIMITED

Inventor： Ian Michael CAULFIELD

IPC: G06F17/30

CPC classification number: G06F16/24578 ,  G06F16/2246

Abstract: An apparatus comprises a reduction tree to rank a given item of a set of M items relative to other items of the set of M items, in dependence on ranking information indicating an order of preference for the set of M items. The reduction tree has a number of levels of node circuits arranged in a tree structure, each node circuit configured to generate a plurality of node output signals indicative of whether a corresponding subset of the set of M items includes at least N more preferred items than the given item, where N≥2. A node circuit at a level of the reduction tree other than a first level is configured to combine the node output signals generated by at least two node circuits at a previous level of the reduction tree, such that the number of items in the corresponding subset increases through successive levels of the reduction tree, until the subset of items corresponding to a root node circuit at a final level of the reduction tree comprises the set of M items.

公开(公告)号：US20180150297A1

公开(公告)日：2018-05-31

申请号：US15578324

申请日：2016-03-31

Applicant: ARM LIMITED

Inventor： Max John BATLEY ,  Simon John CRASKE ,  Ian Michael CAULFIELD ,  Peter Richard GREENHALGH ,  Allan John SKILLMAN ,  Antony John PENTON

IPC: G06F9/30 ,  G06F9/38 ,  G06F1/32

CPC classification number: G06F9/30145 ,  G06F1/3296 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/3885

Abstract: An apparatus (2) has a processing pipeline (4) supporting at least a first processing mode and a second processing mode with different energy consumption or performance characteristics. A storage structure (22, 30, 36, 50, 40, 64, 44) is accessible in both the first and second processing modes. When the second processing mode is selected, control circuitry (70) triggers a subset (102) of the entries of the storage structure to be placed in a power saving state.

公开(公告)号：US20160357561A1

公开(公告)日：2016-12-08

申请号：US15097377

申请日：2016-04-13

Applicant: ARM LIMITED

Inventor： Peter Richard GREENHALGH ,  Simon John CRASKE ,  Ian Michael CAULFIELD ,  Max John BATLEY ,  Allan John SKILLMAN ,  Antony John PENTON

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/30083 ,  G06F9/30058 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3867

Abstract: A processing pipeline may have first and second execution circuits having different performance or energy consumption characteristics. Instruction supply circuitry may support different instruction supply schemes with different energy consumption or performance characteristics. This can allow a further trade-off between performance and energy efficiency. Architectural state storage can be shared between the execute units to reduce the overhead of switching between the units. In a parallel execution mode, groups of instructions can be executed on both execute units in parallel.

Abstract translation: 处理管线可以具有具有不同性能或能量消耗特性的第一和第二执行电路。 指令供应电路可以支持具有不同能量消耗或性能特征的不同指令供给方案。 这可以在性能和能源效率之间进一步权衡。 建筑状态存储可以在执行单元之间共享，以减少单元之间切换的开销。 在并行执行模式中，可以在两个执行单元上并行执行指令组。

公开(公告)号：US20140281423A1

公开(公告)日：2014-09-18

申请号：US13826553

申请日：2013-03-14

Applicant: ARM LIMITED

Inventor： Ian Michael CAULFIELD ,  Peter Richard GREENHALGH ,  Max John BATLEY

IPC: G06F9/30

CPC classification number: G06F9/30079 ,  G06F9/3836 ,  G06F9/3875 ,  G06F9/3885

Abstract: A processor has a processing pipeline with first, second and third stages. An instruction at the first stage takes fewer cycles to reach the second stage then the third stage. The second and third stages each have a duplicated processing resource. For a pending instruction which requires the duplicated resource and can be processed using the duplicated resource at either of the second and third stages, the first stage determines whether a required operand would be available when the pending instruction would reach the second stage. If the operand would be available, then the pending instruction is processed using the duplicated resource at the second stage, while if the operand would not be available in time then the instruction is processed using the duplicated resource in the third pipeline stage. This technique helps to reduce delays caused by data dependency hazards.

Abstract translation: 处理器具有第一，第二和第三阶段的处理流水线。 第一阶段的指令需要更少的周期才能到达第二阶段，然后到第三阶段。 第二和第三阶段各有一个重复的处理资源。 对于要求复制的资源并且可以使用第二级和第三级中的任一级的重复资源来处理的等待指令，第一级确定当待命指令将到达第二级时所需的操作数是否可用。 如果操作数可用，则在第二阶段使用重复的资源处理挂起的指令，而如果操作数在时间上不可用，则使用第三流水线阶段中的重复资源处理指令。 这种技术有助于减少数据依赖性危害造成的延误。

公开(公告)号：US20240036760A1

公开(公告)日：2024-02-01

申请号：US17875758

申请日：2022-07-28

Applicant: Arm Limited

Inventor： Ian Michael CAULFIELD ,  ABHISHEK RAJA ,  Alexander Alfred HORNUNG

IPC: G06F3/06 ,  G06F12/0802

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0671 ,  G06F12/0802 ,  G06F2212/60

Abstract: An apparatus supports decoding and execution of a bulk memory instruction specifying a block size parameter. The apparatus comprises control circuitry to determine whether the block size corresponding to the block size parameter exceeds a predetermined threshold, and performs a micro-architectural control action to influence the handling of at least one bulk memory operation by memory operation processing circuitry. The micro-architectural control action varies depending on whether the block size exceeds the predetermined threshold, and further depending on the states of other components and operations within or coupled with the apparatus. The micro-architectural control action could include an alignment correction action, cache allocation control action, or processing circuitry selection action.

公开(公告)号：US20210311742A1

公开(公告)日：2021-10-07

申请号：US17266759

申请日：2019-07-17

Applicant: Arm Limited

Inventor： Peter Richard GREENHALGH ,  Frederic Claude Marie PIRY ,  Ian Michael CAULFIELD ,  Albin Pierrick TONNERRE

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus and method are provided for processing instructions. The apparatus has execution circuitry for executing instructions, where each instruction requires an associated operation to be performed using one or more source operand values in order to produce a result value. Issue circuitry is used to maintain a record of pending instructions awaiting execution by the execution circuitry, and prediction circuitry is used to produce a predicted source operand value for a chosen pending instruction. Optimisation circuitry is then arranged to detect an optimisation condition for the chosen pending instruction when the predicted source operand value is such that, having regard to the associated operation for the chosen pending instruction, the result value is known without performing the associated operation. In response to detection of the optimisation condition, an optimisation operation is implemented instead of causing the execution circuitry to perform the associated operation in order to execute the chosen pending instruction. This can lead to significant performance and/or power consumption improvements.

公开(公告)号：US20180173535A1

公开(公告)日：2018-06-21

申请号：US15578477

申请日：2016-03-31

Applicant: ARM LIMITED

Inventor： Max John BATLEY ,  Simon John CRASKE ,  Ian Michael CAULFIELD ,  Peter Richard GREENHALGH ,  Allan John SKILLMAN ,  Antony John PENTON

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3885 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/383 ,  G06F9/3851

Abstract: An apparatus comprises prediction circuitry (40, 100, 80) for determining, based on current prediction policy information (43, 82, 104), a predicted behaviour to be used for processing instructions. The current prediction policy information is updated based on an outcome of processing of instructions. A storage structure (50) stores at least one entry identifying previous prediction policy information (60) for a corresponding block of instructions. In response to an instruction from a block having a corresponding entry in the storage structure (50) which identifies the previous prediction policy information (60), the current prediction policy information (43, 82, 104) can be reset based on the previous prediction policy information 60 identified in the corresponding entry of the storage structure (50).

公开(公告)号：US20170147346A1

公开(公告)日：2017-05-25

申请号：US14947030

申请日：2015-11-20

Applicant: ARM LIMITED

Inventor： Alexander Alfred HORNUNG ,  Ian Michael CAULFIELD

IPC: G06F9/30 ,  G06F12/10

Abstract: An apparatus and method are provided for managing a branch information storage. The apparatus has a processor to process instructions, comprising fetch circuitry to fetch instructions from a plurality of threads for processing by the processor. The branch information storage has a plurality of entries, each entry storing a virtual address identifier for a branch instruction, branch information about the branch instruction, and thread identifier information indicating which of the plurality of threads that entry is valid for. The fetch circuitry is arranged to access the branch information storage using a virtual address of an instruction to be fetched for one of the plurality of threads, in order to determine whether a hit condition exists, and in that event to obtain the branch information stored in the entry that gave rise to the hit condition. The apparatus also has address translation circuitry to apply an address translation regime to convert the virtual address into a physical address, at least one address translation regime being specified for each thread. When allocating an entry into the branch information storage, allocation circuitry is arranged to determine, for at least one branch instruction for a current thread, whether the address translation regime is shared with the current thread and at least one other thread. In that event, the allocation circuitry then identifies within the thread identifier information of the allocated entry both the current thread and any other thread for which the address translation regime is shared. Such an approach can significantly alleviate the space constraints on the branch information storage, when employed within an apparatus that supports fine-grained multithreading.

公开(公告)号：US20170017490A1

公开(公告)日：2017-01-19

申请号：US15152781

申请日：2016-05-12

Applicant: ARM LIMITED

Inventor： Ian Michael CAULFIELD

IPC: G06F9/38

CPC classification number: G06F9/3802 ,  G06F9/3836

Abstract: Processing circuitry includes execute circuitry for executing micro-operations in response to instructions fetched from a data store. Control circuitry is provided to determine, based on availability of at least one processing resource, how many micro-operations are to be executed by the execute circuitry in response to a given set of one or more instructions fetched from the data store.

Abstract translation: 处理电路包括响应于从数据存储器取出的指令执行微操作的执行电路。 提供控制电路以根据至少一个处理资源的可用性来确定执行电路响应于从数据存储器提取的一个或多个指令的给定集合执行多少微操作。