公开(公告)号：US10515684B2

公开(公告)日：2019-12-24

申请号：US15823490

申请日：2017-11-27

Applicant: Arm Limited

Inventor： Mohit Chanana ,  Ankur Goel ,  Shruti Aggarwal

IPC: G11C11/413 ,  G11C11/408 ,  G11C11/418 ,  G11C11/419 ,  G11C8/08

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The wordline driver may include multiple transistors. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. Gates of the read assist transistor and at least one transistor of the multiple transistors may be coupled together. While activated, the read assist transistor may provide a read assist signal to the wordline when the wordline is selected and driven by the wordline driver.

公开(公告)号：US20170365331A1

公开(公告)日：2017-12-21

申请号：US15188873

申请日：2016-06-21

Applicant: ARM Limited

Inventor： Mohit Chanana ,  Ankur Goel

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: Various implementations described herein are directed to a device having a memory cell coupled to complementary bitlines. The memory cell may store at least one data bit value associated with complementary bitline signals received via the complementary bitlines. The device may include a pair of write drivers coupled to the memory cell via the complementary bitlines. The pair of write drivers may be arranged to provide the complementary bitline signals to the memory cell based on complementary boost signals. The device may include a pair of complementary boost generators coupled to corresponding gates of the pair of write drivers. The pair of complementary boost generators may be arranged to selectively provide the complementary boost signals to the corresponding gates of the pair of write drivers based on the at least one data bit value.

公开(公告)号：US11017142B1

公开(公告)日：2021-05-25

申请号：US17010630

申请日：2020-09-02

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Shruti Aggarwal ,  Mohit Chanana ,  Hsin-Yu Chen ,  Kyung Woo Kim

IPC: G06F30/343 ,  G06F30/337 ,  G06F30/20 ,  G06F1/28 ,  G06F119/12 ,  G06F119/06 ,  G06F30/3308

Abstract: According to one implementation of the present disclosure, a method includes determining one or more of a read current threshold, a leakage current threshold or a minimum assist voltage threshold; identifying a logic design, wherein the logic design is based the on one or more of the read current threshold, the leakage current threshold, or the minimum assist voltage threshold; identifying a bitcell-type and a corresponding version of the bitcell-type, wherein each version of the bitcell-type is associated with performance and power attributes of a bitcell of a memory array; and determining a memory optimization mode based on the identified logic design and the identified version of the bitcell-type.

公开(公告)号：US20190164590A1

公开(公告)日：2019-05-30

申请号：US15823490

申请日：2017-11-27

Applicant: Arm Limited

Inventor： Mohit Chanana ,  Ankur Goel ,  Shruti Aggarwal

IPC: G11C11/408 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/4085 ,  G11C8/08 ,  G11C11/4087 ,  G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The wordline driver may include multiple transistors. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. Gates of the read assist transistor and at least one transistor of the multiple transistors may be coupled together. While activated, the read assist transistor may provide a read assist signal to the wordline when the wordline is selected and driven by the wordline driver.

公开(公告)号：US10199092B2

公开(公告)日：2019-02-05

申请号：US15188873

申请日：2016-06-21

Applicant: ARM Limited

Inventor： Mohit Chanana ,  Ankur Goel

IPC: G11C11/00 ,  G11C11/419

Abstract: Various implementations described herein are directed to a device having a memory cell coupled to complementary bitlines. The memory cell may store at least one data bit value associated with complementary bitline signals received via the complementary bitlines. The device may include a pair of write drivers coupled to the memory cell via the complementary bitlines. The pair of write drivers may be arranged to provide the complementary bitline signals to the memory cell based on complementary boost signals. The device may include a pair of complementary boost generators coupled to corresponding gates of the pair of write drivers. The pair of complementary boost generators may be arranged to selectively provide the complementary boost signals to the corresponding gates of the pair of write drivers based on the at least one data bit value.