公开(公告)号：US10530562B2

公开(公告)日：2020-01-07

申请号：US15493429

申请日：2017-04-21

Applicant: ARM Limited

Inventor： Richard Andrew Paterson ,  Simon Crossley ,  Ramnath Bommu Subbiah Swamy ,  Steven Douglas Krueger ,  Anitha Kona

IPC: G06F1/12 ,  H04L12/26 ,  H04L7/00

Abstract: A method for correlating first and second local time counts in first and second integrated circuits is provided. The first and second integrated circuits communicate via a communication network. A separate time control signal path is also provided between the integrated circuits. The method comprises determining a signal propagation latency associated with propagation of a latency determining signal between the integrated circuits on the time control signal path, and correlating the first and second local time counts in dependence on the signal propagation latency and a time correlating signal transmitted on the time control signal path.

公开(公告)号：US11841800B2

公开(公告)日：2023-12-12

申请号：US17225614

申请日：2021-04-08

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Jamshed Jalal ,  Steven Douglas Krueger ,  Klas Magnus Bruce

IPC: G06F12/08 ,  G06F12/0842 ,  G06F12/10 ,  G06F13/40

CPC classification number: G06F12/0842 ,  G06F12/10 ,  G06F13/4027 ,  G06F2212/1024 ,  G06F2212/608

Abstract: An apparatus and method for handling stash requests are described. The apparatus has a processing element with an associated storage structure that is used to store data for access by the processing element, and an interface for coupling the processing element to interconnect circuitry. Stash request handling circuitry is also provided that, in response to a stash request targeting the storage structure being received at the interface from the interconnect circuitry, causes a block of data associated with the stash request to be stored within the storage structure. The stash request identifies a given address that needs translating into a corresponding physical address in memory, and also identifies an address space key. Address translation circuitry is used to convert the given address identified by the stash request into the corresponding physical address by performing an address translation that is dependent on the address space key identified by the stash request. The stash request handling circuitry is then responsive to the corresponding physical address determined by the address translation circuitry to cause the block of data to be stored at a location within the storage structure associated with the physical address.

公开(公告)号：US11604733B1

公开(公告)日：2023-03-14

申请号：US17515661

申请日：2021-11-01

Applicant: Arm Limited

Inventor： Steven Douglas Krueger

IPC: G06F12/0864 ,  G06F12/0846 ,  G06F12/0871

Abstract: An apparatus has processing circuitry to perform data processing, at least one architectural register to store at least one partition identifier selection value which is programmable by software processed by the processing circuitry; a set-associative cache comprising a plurality of sets each comprising a plurality of ways; and partition identifier selecting circuitry to select, based on the at least one partition identifier selection value stored in the at least one architectural register, a selected partition identifier to be specified by a cache access request for accessing the set-associative cache. The set-associative cache comprises: selecting circuitry responsive to the cache access request to select, based on the selected partition identifier, a selected cache maximum associativity value; and allocation control circuitry to limit a number of ways allocated in a same set for information associated with the selected partition identifier to a maximum number of ways determined based on the selected cache maximum associativity value.

公开(公告)号：US10268379B2

公开(公告)日：2019-04-23

申请号：US15405691

申请日：2017-01-13

Applicant: ARM Limited

Inventor： Steven Douglas Krueger

IPC: G06F3/06 ,  G06F9/50 ,  G06F9/52 ,  G06F9/455 ,  G06F12/0846 ,  G06F9/46

Abstract: An apparatus comprises two or more partition identifier registers, each corresponding to a respective operating state of processing circuitry and specifying a partition identifier for that operating state. The processing circuitry issues a memory transaction specifying a partition identifier depending on the partition identifier stored in a partition identifier register selected based on the current operating state. The memory system component selects one of a number of sets of memory system component parameters in dependence on the partition identifier specified by a memory transaction to be handled. The memory system component controls allocation of resources for handling the memory transaction or manages contention for the resources in dependence on the selected set of parameters, or updates performance monitoring data specified by the selected set of parameters in response to handling of said memory transaction.

公开(公告)号：US12001705B2

公开(公告)日：2024-06-04

申请号：US17330722

申请日：2021-05-26

Applicant: Arm Limited

Inventor： Seow Chuan Lim ,  Steven Douglas Krueger

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0673

Abstract: An apparatus includes processing circuitry for performing data processing in response to instructions of a software execution environment. Configuration storage circuitry stores a set of memory transaction parameters in association with a partition identifier and configuration application circuitry applies the set of memory transaction parameters in respect of memory transactions issued by the software execution environment that identifies the partition identifier. The memory transaction parameters comprise a minimum target allocation of a resource used by a memory system in handling the memory transaction that identifies the partition identifier. Also provided is an apparatus that comprises processing circuitry for performing data processing in response to instructions of a software execution environment. Configuration storage circuitry stores a set of memory transaction parameters and associated partition identifiers. The memory transaction parameters comprise resource allocations for handling transactions that identify the associated partition identifier. Configuration application circuitry performs the resource allocations. The memory transaction parameters comprise an enable setting and the configuration application circuitry inhibits the resource allocations based on the enable setting.

公开(公告)号：US10664306B2

公开(公告)日：2020-05-26

申请号：US15405625

申请日：2017-01-13

Applicant: ARM Limited

Inventor： Steven Douglas Krueger

IPC: G06F3/06 ,  G06F9/46 ,  G06F9/50 ,  G06F9/52

Abstract: An apparatus is provided comprising processing circuitry to perform data processing in response to instructions of one of a plurality of software execution environments. At least one memory system component handles memory transactions for accessing data, with each memory transaction specifying a partition identifier allocated to a software execution environment associated with the memory transaction. The at least one memory system component is configured to select one of a plurality of sets of memory transaction progression parameters associated with the partition identifier specified by a memory transaction to be handled. Memory transaction progression control circuitry controls progression of the memory transaction in dependence on the selected set of memory transaction progression parameters.

公开(公告)号：US10394454B2

公开(公告)日：2019-08-27

申请号：US15405661

申请日：2017-01-13

Applicant: ARM Limited

Inventor： Steven Douglas Krueger

IPC: G06F3/06 ,  G06F9/455 ,  G06F9/46 ,  G06F9/50 ,  G06F9/52 ,  G06F12/0846

Abstract: Memory transactions are issued to a memory system component specifying a partition identifier allocated to a software execution environment associated with said memory transaction. The memory system component selects one of a plurality of sets of memory system component parameters in dependence on the partition identifier specified by a memory transaction to be handled. The memory system component controls allocation of resources for handling the memory transaction or manages contention for the resources in dependence on the selected set of parameters, or updates performance monitoring data specified by the selected set of parameters in response to handling of said memory transaction. Partition identifier remapping circuitry is provided to remap a virtual partition identifier specified for a memory transaction by a first software execution environment to a physical partition identifier to be specified with the memory transaction issued to the memory system component.

公开(公告)号：US11662931B2

公开(公告)日：2023-05-30

申请号：US17330724

申请日：2021-05-26

Applicant: Arm Limited

Inventor： Seow Chuan Lim ,  Steven Douglas Krueger

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0631 ,  G06F3/0679

Abstract: An apparatus includes processing circuitry configured that performs data processing in response to instructions of one of a plurality of software execution environments. First stage partition identifier remapping circuitry remaps a partition identifier specified for a memory transaction by a first software execution environment to a internal partition identifier to be specified with the memory transaction issued to at least one memory system component. In response to a memory transaction to be handled, the at least one memory system component controls allocation of resources for handling the memory transaction or manage contention for the resources in dependence on a selected set of memory system component parameters selected in dependence on the internal partition identifier specified by the memory transaction. Second stage partition identifier remapping circuitry dynamically overrides the internal partition identifier to be specified with the memory transaction based on a sideband input signal and the first stage partition identifier remapping circuitry indicates, for the partition identifier, whether the second stage partition identifier remapping circuitry is to be used.

公开(公告)号：US11620217B2

公开(公告)日：2023-04-04

申请号：US17218718

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Steven Douglas Krueger ,  Yuval Elad

IPC: G06F12/0802 ,  G06F3/06

Abstract: Processing circuitry processes instructions in one of at least three domains each associated with a corresponding physical address space, and issues a memory access request to a memory system, the memory access request comprising a partition identifier (selected based on programmable partition identifier selection information associated with a current software execution environment which caused the memory access request to be issued) and a multi-bit partition identifier space indicator indicating a selected partition identifier space (selected from among at least three partition identifier spaces based on a current domain of the processing circuitry). The selected partition identifier space and partition identifier together represent information for selecting, at a memory system component, parameters for controlling allocation of resources for handling the memory access request or managing contention for said resources, or for selecting whether performance monitoring data is updated in response to the memory access request.

公开(公告)号：US11442771B2

公开(公告)日：2022-09-13

申请号：US16732654

申请日：2020-01-02

Applicant: Arm Limited

Inventor： Steven Douglas Krueger

IPC: G06F9/50 ,  G06F9/46 ,  G06F3/06 ,  G06F9/54 ,  G06F11/07

Abstract: Memory transactions can be tagged with a partition identifier selected depending on which software execution environment caused the memory transaction to be issued. A memory system component can control allocation of resources for handling the memory transaction or manage contention for said resources depending on a selected set of memory system component parameters selected depending on the partition identifier specified by the memory transaction. Programmable constraint storage circuitry stores at least one resource control parameter constraint used to constrain updating or usage of memory system component resource control parameters.