公开(公告)号：US10853165B2

公开(公告)日：2020-12-01

申请号：US16281388

申请日：2019-02-21

Applicant: Arm Limited

Inventor： Zheng Xu

IPC: G06F11/10

Abstract: An apparatus for providing fault resilience has storage for providing a plurality of compare data blocks, and processing circuitry that performs, for each compare data block, a processing operation using the input data and the compare data block to produce a match condition indication for that compare data block. Performance of the processing operation for each compare data block should result in only one match condition indication indicating a match. Evaluation circuitry evaluates the match condition indications produced for the plurality of compare data blocks and is arranged, in the presence of only one match condition indication indicating a match, to perform a false hit check procedure in order to check for presence of a false hit. In the presence of the false hit, the evaluation circuitry produces an error indication as the outcome indication, but otherwise produces a hit indication as the outcome indication.

公开(公告)号：US10796040B2

公开(公告)日：2020-10-06

申请号：US16267498

申请日：2019-02-05

Applicant: Arm Limited

Inventor： Sean James Salisbury ,  Zheng Xu ,  Arthur Brian Laughton ,  Charles Filip Brej

IPC: G06F30/30 ,  G06F30/394 ,  G06F30/398 ,  G06F9/30

Abstract: A method comprises generating, using a computer, an integrated circuit layout including a plurality of data handling nodes interconnected by routing circuitry defining data packet routes between the plurality of data handling nodes; for a transaction source node configured to generate data packets associated with a data handling translation between that transaction source node and a transaction target node and having one or more routing data fields controlling routing of the data packet, detecting, using the computer, a difference between a first routing controlled by the one or more routing data fields and a selected second routing provided by the integrated circuit layout; and providing, using the computer, one or more data mapping nodes in the integrated circuit layout to map an initial value of one or more of the routing data fields of a data packet generated by the transaction source node to a mapped data value, so that the mapped data value controls routing of the data packet using the selected second routing.

公开(公告)号：US20200267073A1

公开(公告)日：2020-08-20

申请号：US16280220

申请日：2019-02-20

Applicant: Arm Limited

Inventor： Nitin Kumar Agarwal ,  Zheng Xu ,  Anup Gangwar

IPC: H04L12/751

Abstract: Virtual channel assignment in a network is achieved by constructing a Traffic Conflict Graph (TCG) dependent upon a network interconnect topology. The TCG has vertices corresponding to traffic entries in a network specification and edges that connect pairs of vertices. An edge weight, dependent upon interconnect topology and traffic flow characteristics, is assigned to each edge. The vertices are colored using minimum or soft coloring and the virtual channels are mapped to the traffic entries, according to the resulting colors, to provide a virtual channel assignment. The TCG may be constructed by generating a vertex in the TCG to represent each traffic entry, assigning a traffic flow characteristic of a traffic entry to a corresponding vertex and generating an edge between first and second vertices when a number of ‘qualified’ common edges, across all routes for corresponding traffic entries, is greater than zero.

公开(公告)号：US10545893B1

公开(公告)日：2020-01-28

申请号：US16245337

申请日：2019-01-11

Applicant: Arm Limited

Inventor： Zheng Xu ,  Abdul Ghani Kanawati ,  Timothy Nicholas Hay

IPC: G06F13/26 ,  G06F11/16 ,  G06F15/17 ,  G06F11/20

Abstract: An interrupt controller, and method of operation of such an interrupt controller, are provided. The interrupt controller has an interrupt source interface for receiving interrupts from one or more interrupt sources, and a plurality of output interfaces, where each output interface is associated with a processing device that can execute an interrupt service routine to process an interrupt request issued to that processing device. The interrupt source interface has transaction generation circuitry to generate, for each received interrupt, an original transaction to represent the interrupt and a duplicate transaction to represent the interrupt. Buffer circuitry then buffers the original transaction and the duplicate transaction for each received interrupt, and selection circuitry is provided for selecting transactions from the buffer circuitry, and for routing each selected transaction for receipt by the output interface identified by an address portion of the selected transaction. Each output interface has queue storage comprising a plurality of queue entries, where each queue entry is allocated to a transaction received by the output interface and is used to store interrupt identifying information provided by a data portion of the transaction. The queue storage is arranged to maintain duplication tracking information to identify when both the original transaction and its associated duplicate transaction have been received by the output interface. Each output interface inhibits issuing an output signal that would cause an interrupt request for the original transaction to be sent to the associated processing device, until the duplication tracking information identifies that both the original transaction and the associated duplicate transaction have been received by that output interface. This provides an efficient functional safety compliant design for an interrupt controller.

公开(公告)号：US11010241B2

公开(公告)日：2021-05-18

申请号：US16243168

申请日：2019-01-09

Applicant: Arm Limited

Inventor： Zheng Xu ,  Abdul Ghani Kanawati ,  Viswanath Chakrala

IPC: G06F11/10 ,  G06F12/10 ,  G06F11/00 ,  G06F11/16 ,  G06F12/14 ,  G06F11/07 ,  G06F13/40

Abstract: An apparatus and method of operating the apparatus are disclosed, where the apparatus has translation circuitry to perform translations of input data to generate a translation response comprising translated data. The translation is performed in dependence on translation configuration data stored in data storage. A processing element determines an associated error detection code in dependence on the input data and on the translated data, and causes the translation configuration data and the associated error detection code to be stored in the data storage. When translation of the input data is performed by the translation circuitry the translation configuration data and its associated error detection code are retrieved from the data storage and the input data is translated into the translated data in dependence on the translation configuration data. A verification error detection code is calculated in dependence on the input data and on the translated data. A difference between the associated error detection code and the verification error detection code triggers an error in the translation response.

公开(公告)号：US10771194B2

公开(公告)日：2020-09-08

申请号：US15989226

申请日：2018-05-25

Applicant: Arm Limited

Inventor： Andrew David Tune ,  Guanghui Geng ,  Zheng Xu

IPC: H04L1/00 ,  H04L12/707 ,  G06F13/40 ,  G06F17/50 ,  G06F30/30

Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.

公开(公告)号：US10791045B2

公开(公告)日：2020-09-29

申请号：US16280220

申请日：2019-02-20

Applicant: Arm Limited

Inventor： Nitin Kumar Agarwal ,  Zheng Xu ,  Anup Gangwar

IPC: H04L12/751 ,  H04L12/721 ,  H04W72/04

Abstract: Virtual channel assignment in a network is achieved by constructing a Traffic Conflict Graph (TCG) dependent upon a network interconnect topology. The TCG has vertices corresponding to traffic entries in a network specification and edges that connect pairs of vertices. An edge weight, dependent upon interconnect topology and traffic flow characteristics, is assigned to each edge. The vertices are colored using minimum or soft coloring and the virtual channels are mapped to the traffic entries, according to the resulting colors, to provide a virtual channel assignment. The TCG may be constructed by generating a vertex in the TCG to represent each traffic entry, assigning a traffic flow characteristic of a traffic entry to a corresponding vertex and generating an edge between first and second vertices when a number of ‘qualified’ common edges, across all routes for corresponding traffic entries, is greater than zero.