公开(公告)号：US11314675B2

公开(公告)日：2022-04-26

申请号：US16659762

申请日：2019-10-22

Applicant: Arm Limited

Inventor： Guanghui Geng ,  Andrew David Tune ,  Daniel Adam Sara ,  Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40 ,  G06F12/0888 ,  G06F12/0815

Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.

公开(公告)号：US10761561B2

公开(公告)日：2020-09-01

申请号：US15989228

申请日：2018-05-25

Applicant: Arm Limited

Inventor： Saira Samar Malik ,  David Joseph Hawkins ,  Andrew David Tune ,  Guanghui Geng ,  Julian Jose Hilgemberg Pontes

IPC: G06F1/12 ,  G06F30/39

Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.

公开(公告)号：US10579469B2

公开(公告)日：2020-03-03

申请号：US15989224

申请日：2018-05-25

Applicant: Arm Limited

Inventor： Guanghui Geng ,  Andrew David Tune

IPC: G06F7/02 ,  H03M13/00 ,  G06F11/10 ,  G06F13/40

Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.

公开(公告)号：US10771194B2

公开(公告)日：2020-09-08

申请号：US15989226

申请日：2018-05-25

Applicant: Arm Limited

Inventor： Andrew David Tune ,  Guanghui Geng ,  Zheng Xu

IPC: H04L1/00 ,  H04L12/707 ,  G06F13/40 ,  G06F17/50 ,  G06F30/30

Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.

公开(公告)号：US20190361770A1

公开(公告)日：2019-11-28

申请号：US15989224

申请日：2018-05-25

Applicant: Arm Limited

Inventor： Guanghui Geng ,  Andrew David Tune

IPC: G06F11/10 ,  G06F13/40

Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.

公开(公告)号：US12099456B2

公开(公告)日：2024-09-24

申请号：US18098360

申请日：2023-01-18

Applicant: Arm Limited

Inventor： Guanghui Geng ,  Andrew Brookfield Swaine

IPC: G06F13/16 ,  G06F12/1027 ,  G06F12/14 ,  G06F13/22

CPC classification number: G06F13/1689 ,  G06F12/1027 ,  G06F12/1491 ,  G06F13/225

Abstract: Circuitry comprises a memory to store data defining a set of one or more command queues each associated with a respective memory address space, each command queue defining successive commands for execution from a queue head to a queue tail, the commands being selected from a set of commands comprising synchronization commands and one or more other commands defining memory management operations for a given memory address space, in which completion of a synchronization command is dependent upon one or more completion criteria indicating that all commands from any of the command queues which are earlier than the synchronization command in an execution order have completed; and command processing circuitry to execute the commands; in which the command processing circuitry is configured to maintain a linked list of entries having a list order, each entry defining a respective one of the command queues, in which the command processing circuitry is configured to execute commands at the head of command queues, the command queues being defined by prevailing entries of the linked list of entries in the list order; and in which, for a current occupancy of the linked list at a given stage, the given stage being a given stage of executing commands from command queues defined by entries of the linked list, the command processing circuitry is configured to execute a synchronization command first in the list order and to detect, within that current occupancy of the linked list at the given stage, any further synchronization commands at the head of command queues which are defined by entries of the linked list later in the list order, the command processing circuitry applying, for any such further synchronization commands, the completion criteria of the synchronization command at the head of a given command queue, the given command queue being defined by an entry of the linked list earliest in the list order so as to treat any such further synchronization commands as having been completed.

公开(公告)号：US11281403B2

公开(公告)日：2022-03-22

申请号：US16830749

申请日：2020-03-26

Applicant: Arm Limited

Inventor： Thomas Franz Gaertner ,  Viswanath Chakrala ,  Guanghui Geng

IPC: G06F3/06

Abstract: Circuitry comprises attribute storage circuitry having a plurality of entries to hold data defining at least a transaction attribute of one or more respective data handling transactions initiated by transaction source circuitry; comparator circuitry to compare a transaction attribute of a given data handling transaction with data held by the attribute storage circuitry to detect whether the given data handling transaction would be resolved by any data handling transaction for which attribute data is held by a respective entry in the attribute storage circuitry; and control circuitry to associate the given data handling transaction with the respective entry in the attribute storage circuitry to form a set of associated data handling transactions when the comparator circuitry detects that the given data handling transaction would be fulfilled by the data handling transaction for which attribute data is held by the respective entry in the attribute storage circuitry; the control circuitry comprising output circuitry responsive to a resolution of a data handling transaction in the set of associated data handling transactions, to provide that resolution to the transaction source circuitry as a resolution of each of the set of associated transactions.

公开(公告)号：US09906440B2

公开(公告)日：2018-02-27

申请号：US14734367

申请日：2015-06-09

Applicant: ARM LIMITED

Inventor： Rakesh Raman ,  Andrew David Tune ,  Guanghui Geng

IPC: H04L12/937 ,  H04L12/753 ,  G06F13/14

CPC classification number: H04L45/48 ,  G06F13/14

Abstract: Arbitrating and multiplexing circuitry 28 comprises arbitrating tree circuitry having X arbitrating levels and multiplexing tree circuitry having Y multiplexing levels. The Y multiplexing levels comprise a first set of multiplexing levels upstream of a second set of multiplexing levels. The first set of multiplexing levels operate in parallel with at least some of the arbitrating levels. The second set of multiplexing levels operate in series with the X arbitrating levels such that the second set of multiplexing levels completes the required selection to provide the final output following completion of, and in dependence upon, the arbitration by the arbitrating tree circuitry.