公开(公告)号：US07107424B1

公开(公告)日：2006-09-12

申请号：US10809733

申请日：2004-03-25

申请人： Armen D. Avakian ,  Adam C. Peltz ,  Krzysztof Dobecki ,  Gregory S. Robidoux

发明人： Armen D. Avakian ,  Adam C. Peltz ,  Krzysztof Dobecki ,  Gregory S. Robidoux

IPC分类号： G06F13/00 ,  G06F13/43 ,  G11C7/00 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08

CPC分类号： G06F13/4243

摘要： A method for determining a read strobe pulse delay for data read from a memory having a plurality of memory chips. Each one of the chips provides data along with an associated read strobe pulse. The data read from each one of the plurality of chips is stored in a corresponding one of a plurality of storage devices in response to the read strobe pulse associated with such one of the plurality of chips. A training system determines a delay which when applied in to the plurality of read strobe pulses enables valid read data from the plurality of memory chips to be stored in each one of the plurality of the storage device in response to the read strobe pulses being delayed by the read pulse strobe delay. A process is used to enable preservation of the user data during the training process for use subsequent to the training process.

摘要翻译： 一种用于确定从具有多个存储器芯片的存储器读取的数据的读选通脉冲延迟的方法。 每个芯片都提供数据以及相关的读选通脉冲。 响应于与多个芯片中的一个芯片相关联的读选通脉冲，从多个芯片中的每一个读取的数据被存储在多个存储设备中的对应的一个中。 训练系统确定延迟，当应用于多个读取选通脉冲时，响应于读取的选通脉冲被延迟，多个存储器芯片中的有效读取数据被存储在多个存储器件的每一个中 读脉冲选通延时。 一个过程用于在训练过程中保持用户数据，以便在训练过程之后使用。

公开(公告)号：US07016240B1

公开(公告)日：2006-03-21

申请号：US10809732

申请日：2004-03-25

申请人： Armen D. Avakian ,  Adam C. Peltz ,  Gregory S. Robidoux

发明人： Armen D. Avakian ,  Adam C. Peltz ,  Gregory S. Robidoux

IPC分类号： G11C7/00

CPC分类号： G06F13/1689

摘要： A method for determining a read strobe pulse delay for data read from a memory having a plurality of memory chips. Each one of the chips provides data along with an associated read strobe pulse. The data read from each one of the plurality of chips is stored in a corresponding one of a plurality of storage devices in response to the read strobe pulse associated with such one of the plurality of chips. A training system determines a delay which when applied in to the plurality of read strobe pulses enables valid read data from the plurality of memory chips to be stored in each one of the plurality of the storage device in response to the read strobe pulses being delayed by the read pulse strobe delay. A process is used to enable preservation of the user data during the training process for use subsequent to the training process.

摘要翻译： 一种用于确定从具有多个存储器芯片的存储器读取的数据的读选通脉冲延迟的方法。 每个芯片都提供数据以及相关的读选通脉冲。 响应于与多个芯片中的一个芯片相关联的读选通脉冲，从多个芯片中的每一个读取的数据被存储在多个存储设备中的对应的一个中。 训练系统确定延迟，当应用于多个读取选通脉冲时，响应于读取的选通脉冲被延迟，多个存储器芯片中的有效读取数据被存储在多个存储器件的每一个中 读脉冲选通延时。 一个过程用于在训练过程中保持用户数据，以便在训练过程之后使用。