公开(公告)号：US06661797B1

公开(公告)日：2003-12-09

申请号：US09514725

申请日：2000-02-28

申请人： Ashish Goel ,  Deepak Kataria ,  Dimitris Logothetis ,  Kajamalai Gopalaswamy Ramakrishnan

发明人： Ashish Goel ,  Deepak Kataria ,  Dimitris Logothetis ,  Kajamalai Gopalaswamy Ramakrishnan

IPC分类号： H04L1228

CPC分类号： H04L45/00 ,  H04L45/121

摘要： Arrangements and methods for efficiently selecting an optimum connection path that meets user specified delay requirements with enhanced efficiency. In a basic aspect, a method is implemented by one of a plurality of algorithms to meet user QoS specifications. The user not only specifies a delay threshold T for the incoming request but also specifies a delay threshold tolerance &egr; for the path delay that will satisfy him. Two implementations are disclosed. The first is termed non-iterative and sets scaling factor &tgr;=min (T, (n−1)/&egr;), where n is a number of links in a shortest path, scales all the relevant delay parameters by &tgr;/T, truncates all the scaled values to integers, and uses a dynamic programming algorithm to accumulate the total of resulting link delay parameters values for each possible shortest path. The second method, termed iterative, is similar, except that it sets &tgr;

摘要翻译： 有效选择满足用户指定的延迟要求并提高效率的最佳连接路径的安排和方法。 在一个基本方面，一种方法由多种算法中的一种来实现，以满足用户QoS规范。 用户不仅为传入请求指定了延迟阈值T，还指定了将满足他的路径延迟的延迟阈值容差ε。 公开了两种实现方式。 第一个称为非迭代，并设置缩放因子τt = min（T，（n-1）/ epsilon），其中n是最短路径中的链路数，将所有相关延迟参数缩放为tau / T，截断 将所有缩放的值作为整数，并使用动态编程算法来累积每个可能的最短路径的结果链路延迟参数值的总和。 称为迭代的第二种方法是类似的，只是它设置tau << T。 然后，如果缩放，截断和累加步骤不能满足客户规格，则下一次迭代将两倍。 两种方法都以计算有效的方式计算从一个源到所有目的地的路径。

公开(公告)号：US06385172B1

公开(公告)日：2002-05-07

申请号：US09272720

申请日：1999-03-19

申请人： Deepak Kataria ,  Dimitris Logothetis ,  Santhanam Srinivasan ,  Malathi Veeraraghavan

发明人： Deepak Kataria ,  Dimitris Logothetis ,  Santhanam Srinivasan ,  Malathi Veeraraghavan

IPC分类号： H04J116

CPC分类号： H04L45/00 ,  H04L45/124 ,  H04Q3/0016 ,  H04Q2213/13003 ,  H04Q2213/1305 ,  H04Q2213/1307 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/1313 ,  H04Q2213/13164 ,  H04Q2213/13166 ,  H04Q2213/13176 ,  H04Q2213/13178 ,  H04Q2213/13299 ,  H04Q2213/13335 ,  H04Q2213/13349 ,  H04Q2213/1338

摘要： Methods and communication networks having a plurality of connection-oriented switches in which administrative weights are assigned based on link call blocking probabilities. Three assignment schemes include, first, a solution that can be built in the switch software of sufficiently similar switches to enable the switches to determine administrative weights for their links. The second and third schemes employ administrative weight management stations. The second scheme uses an administrative weight management station that operates to enhance total network revenue or throughput in a communication network in which all of the switches implement a certain type of accounting management information databases (MIB). The third scheme uses an administrative weight management station that computes administrative weights for switches that do not have the capability for the second scheme, but which employ appropriate MIBs.

摘要翻译： 具有多个面向连接的交换机的方法和通信网络，其中基于链路呼叫阻塞概率来分配管理权重。 三种分配方案首先包括可以在交换机软件中构建足够相似的交换机的解决方案，以使交换机能够确定其链路的管理权重。 第二和第三种方案采用行政权重管理站。 第二种方案使用管理权重管理站，其操作以增强其中所有交换机实现某种类型的会计管理信息数据库（MIB）的通信网络中的总网络收入或吞吐量。 第三种方案使用管理权重管理站，其计算对于不具有第二方案的能力但是使用适当的MIB的交换机的管理权重。

公开(公告)号：US06687229B1

公开(公告)日：2004-02-03

申请号：US09188023

申请日：1998-11-06

申请人： Deepak Kataria ,  Dimitris Logothetis ,  Santhanam Srinivasan ,  Malathi Veeraraghavan

发明人： Deepak Kataria ,  Dimitris Logothetis ,  Santhanam Srinivasan ,  Malathi Veeraraghavan

IPC分类号： H04L1226

CPC分类号： H04L45/10 ,  H04L45/121

摘要： Arrangements and methods for improving the probability of finding a connection path that meets user specified delay requirements. The improvements offer packet switches enhanced path selection that will improve the resource utilization of networks, both flat networks and hierarchical networks incorporating such switches. The latter type of networks run the path selection algorithm in the PNNI v1.0 standard where the packet switches are asynchronous transfer mode switches. Two modes of enhanced delay-based path selection are based on two different accumulation methods, namely an additive method and an asymptotic method.

摘要翻译： 用于提高查找符合用户指定延迟要求的连接路径的概率的安排和方法。 这些改进提供了分组交换机增强的路径选择，其将改善网络（包括平面网络和并入这种交换机的分层网络）的资源利用。 后一种类型的网络运行PNNI v1.0标准中的路径选择算法，其中分组交换机是异步传输模式交换机。 两种增强型延迟路径选择模式基于两种不同的累积方法，即加法法和渐近法。

公开(公告)号：US20080080563A1

公开(公告)日：2008-04-03

申请号：US11536848

申请日：2006-09-29

申请人： Deepak Kataria ,  Chengzhou Li

发明人： Deepak Kataria ,  Chengzhou Li

IPC分类号： H04J3/06

CPC分类号： H04J3/0664 ,  H03L7/08 ,  H03L2207/50

摘要： Methods and apparatus for synchronizing a first clock of a transmit node and a second clock of a receive node in a packet network are provided. Receive time stamps are generated for transferred packets at a receive node in-accordance with the second clock. Propagation delay variation is filtered from receive time stamp intervals through a filter in accordance with a frequency of the second clock. The filtered receive time stamp intervals and transmit time stamp intervals of the transferred packets are input into a phase locked loop to generate a new frequency for the second clock. The filter and the second clock are updated in accordance with the new frequency for synchronization with the first clock of the transfer node.

摘要翻译： 提供了用于在分组网络中同步发送节点的第一时钟和接收节点的第二时钟的方法和装置。 根据第二个时钟在接收节点处为传输的分组生成接收时间戳。 根据第二时钟的频率，通过滤波器从接收时间戳间隔过滤传播延迟变化​​。 经过滤波的接收时间戳间隔和传送的分组的传输时间戳间隔被输入到锁相环以产生第二时钟的新频率。 根据用于与传送节点的第一时钟同步的新频率来更新滤波器和第二时钟。

公开(公告)号：US07177279B2

公开(公告)日：2007-02-13

申请号：US10131577

申请日：2002-04-24

申请人： Deepak Kataria

发明人： Deepak Kataria

IPC分类号： H04J3/14

CPC分类号： H04L12/5601 ,  H04L2012/5648 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/5682

摘要： In one embodiment, an apparatus for coordinating merging of packets for one or more virtual circuits (VGs). Each packet of a VC comprising a sequence of cells terminates with an end of packet (EOP) cell. The apparatus comprises one or more buffers, a buffer controller, and a merge processor. Each buffer is configured to receive cells of an associated VC and a threshold value based on traffic of the VC. When a number of cells of a packet in a buffer exceeds the corresponding dynamic threshold value, a corresponding flag of the buffer is set. The buffer controller is configured to drop all cells of the current packet in response to a set flag of a corresponding buffer. The merge processor services each buffer in accordance with a scheduling method to transfer one or more packets from each buffer to an output packet stream.

摘要翻译： 在一个实施例中，一种用于协调用于一个或多个虚拟电路（VG）的分组的合并的装置。 包含单元序列的VC的每个包终止于包（EOP）单元的结尾。 该装置包括一个或多个缓冲器，缓冲器控制器和合并处理器。 每个缓冲器被配置为基于VC的流量接收相关联的VC的小区和阈值。 当缓冲器中的分组的小区的数量超过相应的动态阈值时，设置缓冲器的相应标志。 缓冲器控制器被配置为响应于相应缓冲器的设置标志来丢弃当前分组的所有单元。 合并处理器根据调度方法为每个缓冲器服务以将一个或多个分组从每个缓冲器传送到输出分组流。

公开(公告)号：US20080175270A1

公开(公告)日：2008-07-24

申请号：US11625884

申请日：2007-01-23

申请人： Deepak Kataria ,  Chengzhou Li

发明人： Deepak Kataria ,  Chengzhou Li

IPC分类号： H04J3/22

CPC分类号： H04J3/24

摘要： A multi-stage scheduler that provides improved bandwidth utilization in the presence of processor intensive traffic is disclosed. Incoming traffic is separated into multiple traffic flows. Data blocks of the traffic flows are scheduled for access to a processor resource using a first scheduling algorithm, and processed by the processor resource as scheduled by the first scheduling algorithm. The processed data blocks of the traffic flows are scheduled for access to a bandwidth resource using a second scheduling algorithm, and provided to the bandwidth resource as scheduled by the second scheduling algorithm. The multi-stage scheduler in an illustrative embodiment may be implemented in a network processor integrated circuit or other processing device of a communication system.

摘要翻译： 公开了一种在存在处理器密集型业务的情况下提供改进的带宽利用率的多级调度器。 入站流量分为多个流量。 业务流的数据块被调度为使用第一调度算法对处理器资源进行访问，并由处理器资源按照第一调度算法调度进行处理。 业务流的处理数据块被调度为使用第二调度算法对带宽资源进行访问，并且被提供给由第二调度算法调度的带宽资源。 说明性实施例中的多级调度器可以在通信系统的网络处理器集成电路或其他处理设备中实现。

公开(公告)号：US08718040B2

公开(公告)日：2014-05-06

申请号：US11025101

申请日：2004-12-29

申请人： Deepak Kataria ,  Seong-Hwan Kim ,  David P. Sonnier

发明人： Deepak Kataria ,  Seong-Hwan Kim ,  David P. Sonnier

IPC分类号： H04L12/66 ,  H04L29/06 ,  H04L12/56

CPC分类号： H04L65/00 ,  H04L12/18 ,  H04L12/5602 ,  H04L45/00 ,  H04L45/02 ,  H04L47/15 ,  H04L47/263 ,  H04L47/70 ,  H04L47/762 ,  Y02D50/10

摘要： An integrated circuit device for use in a line card of a network node of a digital networking system is provided. The integrated circuit device is capable of intercepting one or more control messages from at least one CPE device. The one or more control messages correspond to at least an operational status of at least one TE device associated with the at least one CPE device. The integrated circuit device is also capable of transmitting one or more rate control messages to a network processor of the network node to adapt bandwidth utilization and provide adapted data traffic flow to at least one CPE device in relation to the operational status of the at least one TE device.

摘要翻译： 提供一种用于数字网络系统的网络节点的线路卡的集成电路装置。 集成电路设备能够拦截来自至少一个CPE设备的一个或多个控制消息。 一个或多个控制消息对应于与至少一个CPE设备相关联的至少一个TE设备的至少一个操作状态。 集成电路设备还能够将一个或多个速率控制消息发送到网络节点的网络处理器，以适应带宽利用率，并且相对于至少一个CPE设备的操作状态向至少一个CPE设备提供适配的数据业务流 TE设备。

公开(公告)号：US07711009B2

公开(公告)日：2010-05-04

申请号：US11536848

申请日：2006-09-29

申请人： Deepak Kataria ,  Chengzhou Li

发明人： Deepak Kataria ,  Chengzhou Li

IPC分类号： H04J3/06

CPC分类号： H04J3/0664 ,  H03L7/08 ,  H03L2207/50

摘要： Methods and apparatus for synchronizing a first clock of a transmit node and a second clock of a receive node in a packet network are provided. Receive time stamps are generated for transferred packets at a receive node in-accordance with the second clock. Propagation delay variation is filtered from receive time stamp intervals through a filter in accordance with a frequency of the second clock. The filtered receive time stamp intervals and transmit time stamp intervals of the transferred packets are input into a phase locked loop to generate a new frequency for the second clock. The filter and the second clock are updated in accordance with the new frequency for synchronization with the first clock of the transfer node.

摘要翻译： 提供了用于在分组网络中同步发送节点的第一时钟和接收节点的第二时钟的方法和装置。 根据第二个时钟在接收节点处为传输的分组生成接收时间戳。 根据第二时钟的频率，通过滤波器从接收时间戳间隔过滤传播延迟变化​​。 经过滤波的接收时间戳间隔和传送的分组的传输时间戳间隔被输入到锁相环以产生第二时钟的新频率。 根据用于与传送节点的第一时钟同步的新频率来更新滤波器和第二时钟。

公开(公告)号：US07633962B2

公开(公告)日：2009-12-15

申请号：US11193799

申请日：2005-07-29

申请人： Deepak Kataria ,  Codrut Radu Radulescu

发明人： Deepak Kataria ,  Codrut Radu Radulescu

IPC分类号： H04L12/54

CPC分类号： H04L47/30 ,  H04L45/245 ,  H04L47/34 ,  H04L49/90

摘要： A method of minimizing SID difference of simultaneously transmitted cells in two or more data communication lines is provided. A data transmission speed of each of the two or more data communication lines is identified. A fullness threshold of at least one buffer of two or more buffers in a transmit node is configured in relation to a size of a data cell for transmission. The two or more buffers correspond to respective ones of the two or more data communication lines. The at least one buffer communicates with a given one of the two or more data communication lines having a data transmission speed slower than another of the two or more data communication lines. One or more data cells for transmission are assigned to the two or more buffers of the two or more data communication lines at the transmit node. The one or more data cells are transmitted from the transmit node to a receive node in accordance with the data transmission speeds of the two or more data communication lines. The fullness threshold of the at least one buffer controls assignment of data cells to the at least one buffer during data cell transmission on the given data communication line and minimizes SID difference of simultaneously transmitted cells in the two or more data communication lines.

摘要翻译： 提供了一种使两个或多个数据通信线路中的同时发送的小区的SID差异最小化的方法。 识别两条或多条数据通信线路中的每一条的数据传输速度。 发送节点中的两个或更多个缓冲器的至少一个缓冲器的饱和度阈值被配置为用于传输的数据单元的大小。 两个或更多个缓冲器对应于两个或更多个数据通信线路中的相应的缓冲器。 所述至少一个缓冲器与所述两条或更多条数据通信线路中的给定的一条数据传输速度比所述两条或更多条数据通信线路中的另一条数据传输速度慢。 用于发送的一个或多个数据单元被分配给发送节点处的两个或更多个数据通信线路的两个或更多个缓冲器。 根据两条或多条数据通信线路的数据传输速度，一个或多个数据信元从发送节点发送到接收节点。 所述至少一个缓冲器的饱和度阈值在所述给定数据通信线路上的数据单元传输期间控制数据单元向所述至少一个缓冲器的分配，并且最小化两个或更多个数据通信线路中同时发送的小区的SID差异。

公开(公告)号：US07924857B2

公开(公告)日：2011-04-12

申请号：US11326047

申请日：2006-01-05

申请人： Deepak Kataria ,  Codrut Radu Radulescu

发明人： Deepak Kataria ,  Codrut Radu Radulescu

IPC分类号： H04L12/56

CPC分类号： H04L49/9094 ,  H04L49/90

摘要： A method and apparatus of reorganizing cells received over data communication lines at a receive node is provided. The cells have an initial order identified by monotonically increasing sequence identifiers. The receive node has buffers associated with respective ones of the communication lines. Each of the buffers has an output position. A cell having a smallest sequence identifier is detected from one or more cells at the output positions of the buffers. It is determined if the smallest sequence identifier is sequentially consecutive to a specified sequence identifier. If the smallest sequence identifier is sequentially consecutive to the specified sequence identifier, the cell having the smallest sequence identifier is dequeued from an output position of one of the buffers and the specified sequence identifier is redefined as the smallest sequence identifier.

摘要翻译： 提供了一种在接收节点上通过数据通信线路重新组合接收的小区的方法和装置。 单元具有通过单调增加序列标识符来识别的初始顺序。 接收节点具有与相应通信线路相关联的缓冲器。 每个缓冲器都有一个输出位置。 从缓冲器的输出位置的一个或多个单元检测具有最小序列标识符的单元。 确定最小序列标识符是否与指定的序列标识符顺序连续。 如果最小的序列标识符与指定的序列标识符顺序连续，则具有最小序列标识符的小区从一个缓冲区的输出位置出出，并且将指定的序列标识符重新定义为最小的序列标识符。