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公开(公告)号：US08369520B2
公开(公告)日：2013-02-05
申请号：US12034252
申请日：2008-02-20
申请人： Astrid Elbe , Norbert Janssen , Holger Sedlak
发明人： Astrid Elbe , Norbert Janssen , Holger Sedlak
IPC分类号： H04L9/00
CPC分类号： G06F9/3891 , G06F7/72 , G06F7/723 , G06F9/3879 , G06F9/3885 , G06F21/72 , G06F21/755 , G06F2207/7266
摘要： A cryptography processor includes a central processing unit and a co-processor, the co-processor comprising a plurality of calculating subunits as well as a single control unit which is coupled to each of the plurality of calculating subunits. A cryptographic operation is distributed among the individual calculating subunits in the form of sub-operations by the control unit. The central processing unit, the plurality of calculating subunits and the control unit are integrated on a single chip, the chip comprising a common supply current access for supplying the plurality of calculating subunits and the control unit with current. Due to the arrangement of the calculating subunit in parallel, on the hand, the throughput of the cryptography processor is increased. On the other hand, however, the current profile that may be detected at the supply current access is randomized to such an extent that an attacker can no longer infer numbers processed in the individual calculating subunits.
摘要翻译： 密码处理器包括中央处理单元和协处理器，所述协处理器包括多个计算子单元以及耦合到所述多个计算子单元中的每一个的单个控制单元。 通过控制单元以子操作的形式在各个计算子单元之间分配加密操作。 中央处理单元，多个计算子单元和控制单元集成在单个芯片上，该芯片包括用于向多个计算子单元和控制单元提供电流的公共供电电流访问。 由于并行计算子单元的配置，手段上增加了密码处理器的吞吐量。 然而，另一方面，可以在供应电流访问中检测到的当前简档被随机化到这样的程度，使得攻击者不再能够推断在各个计算子单元中处理的数字。
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公开(公告)号：US20050116740A1
公开(公告)日：2005-06-02
申请号：US11004658
申请日：2004-12-03
申请人： Astrid Elbe , Norbert Janssen , Holger Sedlak
发明人： Astrid Elbe , Norbert Janssen , Holger Sedlak
IPC分类号： H04L9/10 , G06F13/40 , H03K19/0175
CPC分类号： G06F13/4027 , Y02D10/14 , Y02D10/151
摘要： Data processing circuit including a single rail bus having a single rail line, a dual rail bus having a first dual rail line for data bits and a second dual rail line for inverted data bits, and a converter for converting signals on the single rail bus into signals on the dual rail bus and vice versa. The converter has a read driver for transferring signals on the first dual rail line to the single rail bus when the read driver is active, a write driver for transferring the signals on the single rail bus to the first dual rail line when the write driver is active, a producer for producing the signals on the second dual rail line from the signals on the first dual rail line when the write driver is active, and a controller for controlling the drivers so that at most only one driver is active.
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公开(公告)号：US07613763B2
公开(公告)日：2009-11-03
申请号：US11090914
申请日：2005-03-24
申请人： Astrid Elbe , Norbert Janssen , Holger Sedlak
发明人： Astrid Elbe , Norbert Janssen , Holger Sedlak
IPC分类号： G06F7/508
CPC分类号： G06F7/509 , G06F7/503 , G06F7/72 , G06F2207/3872 , G06F2207/7266 , H04L9/003 , H04L9/30 , H04L2209/12
摘要： An apparatus and method for converting a dual-rail input. The apparatus combines two useful operand bits and two auxiliary operand bits so that, in a data mode, two output operands of three output operands have a value which is different from that of the third output operand. In a preparation mode, the three output operands of the apparatus have the same value. The apparatus and method may preferably be employed in a three-operands adder as an interface between a dual-rail three-bits half adder and a sum-carry stage of a two-bits full adder so to achieve the same level of security as a full implementation of the three-operands adder in dual-rail technology, despite the two-bits full adder being implemented in single-rail technology.
摘要翻译： 一种用于转换双轨输入的装置和方法。 该装置组合两个有用的操作数位和两个辅助操作数位，使得在数据模式中，三个输出操作数的两个输出操作数具有与第三输出操作数不同的值。 在准备模式下，设备的三个输出操作数具有相同的值。 该装置和方法可以优选地在三操作数加法器中用作双轨三位半加法器和两比特全加器的和进位级之间的接口，以便实现与 尽管在单轨技术中实现了两位全加器，但双轨技术中三运算加法器的全面实现。
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公开(公告)号：US07428651B2
公开(公告)日：2008-09-23
申请号：US10723432
申请日：2003-11-25
申请人： Astrid Elbe , Norbert Janssen , Holger Sedlak
发明人： Astrid Elbe , Norbert Janssen , Holger Sedlak
CPC分类号： G06K19/073 , G06F1/08 , G06F1/12 , G06F1/3203 , G06F13/405
摘要： An inventive electronic circuit includes central processing means having a clock connection and a data connection, as well as a peripheral unit having a clock connection and a data connection, the clock connection of the peripheral unit being connected to a signal output of a controllable oscillator or to an external clock input. Synchronization means having a first and a second data connection is connected, the first data connection being connected to the data connection of the peripheral unit. In addition a data bus connects the data connection of the CPU and the second data connection of the synchronization means. The clocking of the peripheral unit asynchronous to the central processing unit yields a more effective operation being better adjustable to certain parameters, such as, for example, the application and the energy of the electronic circuit available.
摘要翻译： 本发明的电子电路包括具有时钟连接和数据连接的中央处理装置，以及具有时钟连接和数据连接的外围单元，外围单元的时钟连接连接到可控振荡器的信号输出端 到外部时钟输入。 连接具有第一和第二数据连接的同步装置，第一数据连接被连接到外围单元的数据连接。 此外，数据总线连接CPU的数据连接和同步装置的第二数据连接。 与中央处理单元异步的外围单元的时钟产生更有效的操作，以更好地可调整到某些参数，例如可用的电子电路的应用和能量。
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公开(公告)号：US06999337B2
公开(公告)日：2006-02-14
申请号：US10934301
申请日：2004-09-03
申请人： Astrid Elbe , Wieland Fischer , Norbert Janssen , Tanja Roemer , Holger Sedlak , Jean-Pierre Seifert
发明人： Astrid Elbe , Wieland Fischer , Norbert Janssen , Tanja Roemer , Holger Sedlak , Jean-Pierre Seifert
IPC分类号： G11C11/00
CPC分类号： G11C7/22 , G11C2207/007 , G11C2207/2227
摘要： A register cell includes a first input for a data unit to be written into the register cell. The register cell includes further a second input for a negated data unit to be written into the register cell. A first pair of oppositely coupled inverters as a first storage circuit is adapted to be coupled to the first input. A second pair of oppositely coupled inverters as a second storage circuit is adapted to be coupled to a second input. Using two oppositely coupled pairs of inverters makes it possible to initialize both the first input and the second input of the register either to a high voltage state (precharge) or to a low voltage state (discharge), such that the power consumption of the register cell is homogenized from one working clock to the next.
摘要翻译： 寄存器单元包括要写入寄存器单元的数据单元的第一输入。 寄存器单元还包括要被写入寄存器单元的否定数据单元的第二输入。 作为第一存储电路的第一对相反耦合的反相器适于耦合到第一输入。 作为第二存储电路的第二对相反耦合的反相器适于耦合到第二输入。 使用两个相对耦合的反相器对使得可以将寄存器的第一输入和第二输入初始化为高电压状态（预充电）或低电压状态（放电），使得寄存器的功耗 电池从一个工作时钟均匀化到下一个工作时钟。
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公开(公告)号：US20050097156A1
公开(公告)日：2005-05-05
申请号：US10957536
申请日：2004-10-01
CPC分类号： G06F7/506 , G06F7/5052
摘要： Calculating unit having adder blocks, each having single adders, a carry input, a carry output, and a carry pass output, wherein a signal at the carry pass output is indicative of a carry passing through the adder block. Depending on the carry pass output signal, a clock generator for feeding the adder blocks with operands to be processed is decelerated. A determining unit determines in which of the adder blocks a least significant bit of an operand to be subtracted is disposed. A deactivating unit deactivates a carry pass output of adder block(s) provided for lower order digits with respect to the adder block in which the least significant bit is disposed, and a feeding unit feeds a carry into the carry input of this adder block in which the least significant bit is disposed.
摘要翻译： 具有加法器块的计算单元，每个具有单个加法器，进位输入，进位输出和进位通过输出，其中进位通过输出处的信号指示通过加法器块的进位。 根据进位通过输出信号，用于向加法器块馈送要处理的操作数的时钟发生器减速。 确定单元确定在哪个加法器块中设置要减去的操作数的最低有效位。 去激活单元相对于其中布置最低有效位的加法器块去激活为低位数提供的加法器块的进位通过输出，馈送单元将进位馈送到该加法器块的进位输入 其中最低有效位被布置。
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公开(公告)号：US07831650B2
公开(公告)日：2010-11-09
申请号：US11440725
申请日：2006-05-25
IPC分类号： G06F7/38
CPC分类号： G06F7/722
摘要： In a method for modular multiplication using a multiplication look-ahead process for computing a multiplication shift value and a reduction look-ahead process for computing a reduction shift value, a modulus is first transformed into a transformed modulus that is greater than said modulus. The transformation is carried out such that a predetermined fraction of the transformed modulus has a higher-order digit with a first predetermined value that is followed by at least one low-order digit having a second predetermined value. During the iterative working off of the modular multiplication using the multiplication look-ahead process and the reduction look-ahead process, the transformed modulus is utilized so as to obtain at the end of the iteration a transformed result for the modular multiplication. Finally, the transformed result is re-transformed by modular reduction using the original modulus. By means of the transformation according to the invention, iterative working off of the modular multiplication is simplified so that the modular multiplication can be performed faster.
摘要翻译： 在使用用于计算乘法偏移值的乘法预先处理和用于计算减少移位值的减少预先处理的乘法的方法中，首先将模量转换为大于所述模数的变换模数。 进行变换，使得变换模数的预定分数具有具有第一预定值的高阶数字，其后是具有第二预定值的至少一个低位数字。 在使用乘法预先处理和缩小预先处理进行的乘法迭代处理期间，利用变换的模数，以便在迭代结束时获得用于模数乘法的变换结果。 最后，通过使用原始模数的模块化减少来重新转换变换结果。 通过根据本发明的变换，简化了乘法的迭代处理，使得可以更快地执行模乘。
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8.发明授权Processor and method for a simultaneous execution of a calculation and a copying process 有权用于同时执行计算和复制过程的处理器和方法公开(公告)号：US07426529B2
公开(公告)日：2008-09-16
申请号：US11006519
申请日：2004-12-06
CPC分类号： G06F9/30014
摘要： A processor includes a source register having a source register content, a destination register, a calculating unit for performing a calculation using the source register content, wherein the calculation is performed in several calculation cycles, and wherein in each cycle only one portion of the source register content is useable, a data bus connected to the source register, the destination register and the calculating unit, and a processor controller. The processor controller is operable to supply the source register content in portions to the calculating unit on the one hand and to the destination register on the other hand during the calculation via the data bus, so that after an execution of the calculation the source register content is written into the destination register. Therefore it is possible to obtain a register copy of a source register the destination register via a limited data bus without additional machine cycles for long operands to be processed in portions.
摘要翻译： 处理器包括具有源寄存器内容的源寄存器，目的地寄存器，用于使用源寄存器内容执行计算的计算单元，其中在几个计算周期中执行计算，并且其中在每个周期中，源的一部分 注册内容可用，连接到源寄存器，目的地寄存器和计算单元的数据总线以及处理器控制器。 处理器控制器可操作以在计算期间通过数据总线将源寄存器内容一部分提供给计算单元，另一方面提供给目标寄存器，使得在执行计算之后，源寄存器内容 被写入目的寄存器。 因此，有可能通过有限的数据总线获得源寄存器的寄存器副本，而不需要额外的机器周期来进行部分处理的长操作数。
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公开(公告)号：US07120660B2
公开(公告)日：2006-10-10
申请号：US10662627
申请日：2003-09-15
IPC分类号： G06F7/38
CPC分类号： G06F7/722
摘要： In a method for modular multiplication using a multiplication look-ahead process for computing a multiplication shift value and a reduction look-ahead process for computing a reduction shift value, a modulus is first transformed into a transformed modulus that is greater than said modulus. The transformation is carried out such that a predetermined fraction of the transformed modulus has a higher-order digit with a first predetermined value that is followed by at least one low-order digit having a second predetermined value. During the iterative working off of the modular multiplication using the multiplication look-ahead process and the reduction look-ahead process, the transformed modulus is utilized so as to obtain at the end of the iteration a transformed result for the modular multiplication. Finally, the transformed result is re-transformed by modular reduction using the original modulus. By means of the transformation according to the invention, iterative working off of the modular multiplication is simplified so that the modular multiplication can be performed faster.
摘要翻译： 在使用用于计算乘法偏移值的乘法预先处理和用于计算减少移位值的减少预先处理的乘法的方法中，首先将模量转换为大于所述模数的变换模数。 进行变换，使得变换模数的预定分数具有具有第一预定值的高阶数字，其后是具有第二预定值的至少一个低位数字。 在使用乘法预先处理和缩小预先处理进行的乘法迭代处理期间，利用变换的模数，以便在迭代结束时获得用于模数乘法的变换结果。 最后，通过使用原始模数的模块化减少来重新转换变换结果。 通过根据本发明的变换，简化了乘法的迭代处理，使得可以更快地执行模乘。
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公开(公告)号：US06970899B2
公开(公告)日：2005-11-29
申请号：US10957536
申请日：2004-10-01
CPC分类号： G06F7/506 , G06F7/5052
摘要： Calculating unit having adder blocks, each having single adders, a carry input, a carry output, and a carry pass output, wherein a signal at the carry pass output is indicative of a carry passing through the adder block. Depending on the carry pass output signal, a clock generator for feeding the adder blocks with operands to be processed is decelerated. A determining unit determines in which of the adder blocks a least significant bit of an operand to be subtracted is disposed. A deactivating unit deactivates a carry pass output of adder block(s) provided for lower order digits with respect to the adder block in which the least significant bit is disposed, and a feeding unit feeds a carry into the carry input of this adder block in which the least significant bit is disposed.
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