公开(公告)号：US09442873B2

公开(公告)日：2016-09-13

申请号：US14510529

申请日：2014-10-09

Applicant: Atmel Corporation

Inventor： Laurentiu Birsan ,  Frode Milch Pedersen ,  Nicolas Graffet ,  Stein Danielsen ,  Sebastien Jouin

IPC: G06F13/28 ,  G01R31/08

CPC classification number: G06F13/28

Abstract: Systems and methods for direct memory access are described. One example system includes a memory module that includes a first memory portion that maintains transfer descriptors of direct memory access (DMA) channels, and a second memory portion that maintains transfer descriptors of enabled DMA channels. The system includes a controller coupled to the memory module, the controller includes one or more DMA channels coupled to a system bus, a channel arbiter that selects one of the enabled DMA channels as an active DMA channel for data transfer including re-arbitrating after each burst or beat in a given transfer, and an active channel buffer that receives a transfer descriptor of the active DMA channel from the second memory portion. The controller is configured to write back the transfer descriptor of the active DMA channel into the second memory portion when the active DMA channel loses arbitration.

Abstract translation: 描述用于直接存储器访问的系统和方法。 一个示例系统包括存储器模块，该存储器模块包括保持直接存储器访问（DMA）通道的传送描述符的第一存储器部分和维持已使能的DMA通道的传送描述符的第二存储器部分。 该系统包括耦合到存储器模块的控制器，控制器包括耦合到系统总线的一个或多个DMA通道，通道仲裁器，其选择使能的DMA通道中的一个作为用于数据传输的活动DMA通道，包括在每一个之后重新仲裁 在给定传送中突发或跳动，以及从第二存储器部分接收活动DMA通道的传输描述符的活动通道缓冲器。 控制器被配置为当活动DMA通道失去仲裁时将有效DMA通道的传输描述符写回第二存储器部分。

公开(公告)号：US08880756B1

公开(公告)日：2014-11-04

申请号：US13932925

申请日：2013-07-01

Applicant: Atmel Corporation

Inventor： Laurentiu Birsan ,  Frode Milch Pedersen ,  Nicolas Graffet ,  Stein Danielsen ,  Sebastien Jouin

IPC: G06F13/28 ,  G01R31/08

CPC classification number: G06F13/28

Abstract: Systems and methods for direct memory access are described. One example system includes a memory module that includes a first memory portion that maintains transfer descriptors of direct memory access (DMA) channels, and a second memory portion that maintains transfer descriptors of enabled DMA channels. The system includes a controller coupled to the memory module, the controller includes one or more DMA channels coupled to a system bus, a channel arbiter that selects one of the enabled DMA channels as an active DMA channel for data transfer including re-arbitrating after each burst or beat in a given transfer, and an active channel buffer that receives a transfer descriptor of the active DMA channel from the second memory portion. The controller is configured to write back the transfer descriptor of the active DMA channel into the second memory portion when the active DMA channel loses arbitration.

Abstract translation: 描述用于直接存储器访问的系统和方法。 一个示例系统包括存储器模块，该存储器模块包括保持直接存储器访问（DMA）通道的传送描述符的第一存储器部分和维持已使能的DMA通道的传送描述符的第二存储器部分。 该系统包括耦合到存储器模块的控制器，控制器包括耦合到系统总线的一个或多个DMA通道，通道仲裁器，其选择使能的DMA通道中的一个作为用于数据传输的活动DMA通道，包括在每一个之后重新仲裁 在给定传送中突发或跳动，以及从第二存储器部分接收活动DMA通道的传输描述符的活动通道缓冲器。 控制器被配置为当活动DMA通道失去仲裁时将有效DMA通道的传输描述符写回第二存储器部分。