公开(公告)号：US10317978B2

公开(公告)日：2019-06-11

申请号：US15368808

申请日：2016-12-05

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Romain Oddoart ,  Patrice Menard ,  Mickael Le Dily ,  Thierry Gourbilleau

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/3287 ,  G06F13/16

Abstract: A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode.

公开(公告)号：US09710169B2

公开(公告)日：2017-07-18

申请号：US15223227

申请日：2016-07-29

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Ian Fullerton

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0679 ,  G06F13/1689 ,  G06F13/4217 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.

公开(公告)号：US09513691B2

公开(公告)日：2016-12-06

申请号：US14716983

申请日：2015-05-20

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Romain Oddoart ,  Patrice Menard ,  Mickael Le Dily ,  Thierry Gourbilleau

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3287 ,  G06F13/1673 ,  Y02D10/152

Abstract: A microcontroller is operable in a low-power mode and includes one or more I/O connectors, as well as an I/O controller operable to provide control signals for controlling a state of a particular one of the I/O connectors. The I/O controller is powered off or deactivated during the low-power mode. The microcontroller also includes I/O connector state control logic operable to control the state of the particular one of the I/O connectors in accordance with the control signals from the I/O controller. The I/O connector state control logic includes I/O connector state retention logic that retains states of the control signals and maintains the particular I/O connector in a corresponding state in accordance with the retained control signals while the microcontroller is in the low-power mode.

公开(公告)号：US09952913B2

公开(公告)日：2018-04-24

申请号：US15412198

申请日：2017-01-23

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Stein Danielsen ,  Francois Fosse ,  Thierry Delalande ,  Ivar Holand ,  James Hallman

IPC: G06F13/362 ,  G06F17/30 ,  G06F13/40 ,  G06F13/12 ,  G06F9/52 ,  G06F13/28 ,  G06F13/42

CPC classification number: G06F9/526 ,  G06F11/00 ,  G06F11/004 ,  G06F13/122 ,  G06F13/28 ,  G06F13/362 ,  G06F13/4004 ,  G06F13/4282 ,  G06F17/30362 ,  G06F2201/825

Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

公开(公告)号：US20160335000A1

公开(公告)日：2016-11-17

申请号：US15223227

申请日：2016-07-29

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Ian Fullerton

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0679 ,  G06F13/1689 ,  G06F13/4217 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.

Abstract translation: 从非易失性存储器件接收指示非易失性存储器件的当前访问时间的锁存信号。 访问时间表示非易失性存储器件根据数据请求使数据可用的时间量。 接收总线系统时钟信号。 评估锁存信号，并且基于评估来调整非易失性存储器件的等待状态。 等待状态表示由中央处理单元用于访问非易失性存储器件的总线系统时钟的周期数。 产生基于调整后的等待状态触发的总线系统数据就绪信号。 当触发时，总线系统数据就绪信号表示响应于该请求可用数据。

公开(公告)号：US20160274655A1

公开(公告)日：2016-09-22

申请号：US15171695

申请日：2016-06-02

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Patrice Menard ,  Thierry Gourbilleau

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3203 ,  G06F1/3215 ,  G06F1/3228 ,  G06F1/3243 ,  Y02D10/152

Abstract: A microcontroller system is organized into power domains. A power manager of the microcontroller system can change the power configuration of a power domain based on whether the microcontroller system has asserted a power trigger for any module in the power domain or if any module in the power domain has asserted a power keeper.

公开(公告)号：US09423843B2

公开(公告)日：2016-08-23

申请号：US13624651

申请日：2012-09-21

Applicant: Atmel Corporation

Inventor： Sylvain Garnier ,  Anthony Rouaux ,  Sebastien Jouin ,  Frode Milch Pedersen

IPC: G06F1/24 ,  G06F11/267

CPC classification number: G06F1/24 ,  G06F11/267

Abstract: Systems and techniques for processor reset hold control are described. A described system includes a controller to detect a hold request based on an external reset signal and an external debug signal, and generate a hold signal based on a detection of the hold request, where the hold signal continues after the external reset signal has been discontinued; a system component that is responsive to the external reset signal; a processor that is responsive to the hold signal, where the hold signal causes the processor to enter a reset state and to maintain the reset state after the external reset signal has been discontinued; and a system manager configured to permit external access to the system component while the processor is in the reset state. The controller can be configured to discontinue the hold signal in response to a clear request.

Abstract translation: 描述了处理器复位保持控制的系统和技术。 所描述的系统包括控制器，用于基于外部复位信号和外部调试信号检测保持请求，并且基于对保持信号的检测产生保持信号，其中保持信号在外部复位信号中断之后继续 ; 响应于外部复位信号的系统组件; 响应于所述保持信号的处理器，其中所述保持信号使所述处理器进入复位状态，并且在所述外部复位信号已经中断之后保持所述复位状态; 以及被配置为在处理器处于复位状态时允许对系统组件的外部访问的系统管理器。 控制器可以被配置为响应于明确的请求中断保持信号。

公开(公告)号：US09383807B2

公开(公告)日：2016-07-05

申请号：US14043445

申请日：2013-10-01

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Patrice Menard ,  Thierry Gourbilleau

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3215 ,  G06F1/3228 ,  G06F1/3243 ,  Y02D10/152

Abstract: A microcontroller system is organized into power domains. A power manager of the microcontroller system can change the power configuration of a power domain based on whether the microcontroller system has asserted a power trigger for any module in the power domain or if any module in the power domain has asserted a power keeper.

Abstract translation: 微控制器系统被组织成电源域。 微控制器系统的电源管理器可以基于微控制器系统是否为电源域中的任何模块确定了电源触发，或者如果电源域中的任何模块已经断言电源保持器，则可以改变电源域的电源配置。

公开(公告)号：US20150095681A1

公开(公告)日：2015-04-02

申请号：US14043445

申请日：2013-10-01

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Patrice Menard ,  Thierry Gourbilleau

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3215 ,  G06F1/3228 ,  G06F1/3243 ,  Y02D10/152

Abstract: A microcontroller system is organized into power domains. A power manager of the microcontroller system can change the power configuration of a power domain based on whether the microcontroller system has asserted a power trigger for any module in the power domain or if any module in the power domain has asserted a power keeper.

Abstract translation: 微控制器系统被组织成电源域。 微控制器系统的电源管理器可以基于微控制器系统是否为电源域中的任何模块确定了电源触发，或者如果电源域中的任何模块已经断言电源保持器，则可以改变电源域的电源配置。

公开(公告)号：US10228752B2

公开(公告)日：2019-03-12

申请号：US15082056

申请日：2016-03-28

Applicant: Atmel Corporation

Inventor： Sebastien Jouin ,  Romain Oddoart ,  Patrice Menard ,  Mickael Le Dily ,  Thierry Gourbilleau

IPC: G06F1/32 ,  G06F1/3296 ,  G06F1/26 ,  G06F9/4401 ,  G06F13/24

Abstract: A voltage scaling system can scale a supply voltage while preventing processor access of system components that are rendered unstable from the scaling. A processor receives an instruction to scale a system supply voltage to a target supply voltage. The processor executes the instruction and enters into a sleep mode. The processor can send, to a controller that saves power, an indication that the processor is in the sleep mode. When the processor is in the sleep mode, the processor becomes inactive and cannot access any components, e.g., Flash memory data, of the voltage scaling system. The controller can configure a voltage regulator to scale the system supply voltage to the target supply voltage. Once the target supply voltage is reached, the voltage regulator sends an interrupt to the processor, thereby waking up the processor from the sleep mode.