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    Programmable logic unit
    1.
    发明授权
    Programmable logic unit 有权

    公开(公告)号：US10049071B2

    公开(公告)日：2018-08-14

    申请号：US14795806

    申请日：2015-07-09

    Applicant: Atmel Corporation

    Inventor： Laurentiu Birsan ,  Stein Danielsen

    IPC: H03K19/17 ,  G06F13/42 ,  H03K19/177 ,  G06F13/00 ,  G06F13/40

    Abstract: Programmable logic units are described. A described unit includes one or more input interfaces to receive one or more input signals; logic elements that are individually programmable; one or more output interfaces to provide one or more output signals; and a programmable interconnect array that is configured to selectively form one or more interconnections within the unit based on one or more programming settings. The programmable interconnect array can be programmable to route the one or more input signals from the one or more input interfaces to at least a portion of the logic elements, programmable to route one or more intermediate signals among at least a portion of the logic elements, and programmable to route one or more signals from at least a portion of the logic elements to produce the one or more output signals via the output interface.

    PERIPHERAL REGISTER PARAMETER REFRESHING
    4.
    发明申请
    PERIPHERAL REGISTER PARAMETER REFRESHING 有权
    外围注册参数更新

    公开(公告)号：US20160132445A1

    公开(公告)日：2016-05-12

    申请号：US14538305

    申请日：2014-11-11

    Applicant: Atmel Corporation

    Inventor： Laurentiu Birsan ,  Stein Danielsen

    IPC: G06F13/28 ,  G06F12/10

    CPC classification number: G06F13/287 ,  H03M1/12 ,  H03M1/18

    Abstract: Systems, methods, circuits and computer-readable mediums for peripheral sequencing using an access sequence are disclosed. In some implementations, a control register and status register in a peripheral are initialized with control data for selecting peripheral registers of the peripheral to be refreshed during an access sequence. For each peripheral register to be refreshed during the access sequence: a data register of the peripheral register is accessed; the peripheral register is refreshed; and the status register is updated with a current status of the access sequence. The access sequence is determined to be completed based on contents of the status register.

    Abstract translation: 公开了使用接入序列进行外围排序的系统，方法，电路和计算机可读介质。 在一些实现中，外围设备中的控制寄存器和状态寄存器被初始化为用于在访问序列期间选择要刷新的外设的外设寄存器的控制数据。 对于在访问序列期间要刷新的每个外设寄存器：访问外设寄存器的数据寄存器; 外设寄存器刷新; 并且状态寄存器被更新为访问序列的当前状态。 根据状态寄存器的内容确定访问顺序完成。

    PROGRAMMABLE LOGIC UNIT
    5.
    发明申请
    PROGRAMMABLE LOGIC UNIT 审中-公开
    可编程逻辑单元

    公开(公告)号：US20150309957A1

    公开(公告)日：2015-10-29

    申请号：US14795806

    申请日：2015-07-09

    Applicant: Atmel Corporation

    Inventor： Laurentiu Birsan ,  Stein Danielsen

    IPC: G06F13/42 ,  H03K19/177

    CPC classification number: G06F13/4221 ,  G06F13/00 ,  G06F13/40 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736

    Abstract: Programmable logic units are described. A described unit includes one or more input interfaces to receive one or more input signals; logic elements that are individually programmable; one or more output interfaces to provide one or more output signals; and a programmable interconnect array that is configured to selectively form one or more interconnections within the unit based on one or more programming settings. The programmable interconnect array can be programmable to route the one or more input signals from the one or more input interfaces to at least a portion of the logic elements, programmable to route one or more intermediate signals among at least a portion of the logic elements, and programmable to route one or more signals from at least a portion of the logic elements to produce the one or more output signals via the output interface.

    Abstract translation: 描述可编程逻辑单元。 所描述的单元包括用于接收一个或多个输入信号的一个或多个输入接口; 可单独编程的逻辑元件; 一个或多个输出接口以提供一个或多个输出信号; 以及可编程互连阵列，其被配置为基于一个或多个编程设置选择性地在所述单元内形成一个或多个互连。 可编程互连阵列可以被编程为将一个或多个输入信号从一个或多个输入接口路由到逻辑元件的至少一部分，可编程以在至少一部分逻辑元件之间布线一个或多个中间信号， 并且可编程以将来自至少一部分逻辑元件的一个或多个信号路由以经由输出接口产生一个或多个输出信号。

    Direct memory access controller
    6.
    发明授权
    Direct memory access controller 有权
    直接内存访问控制器

    公开(公告)号：US09442873B2

    公开(公告)日：2016-09-13

    申请号：US14510529

    申请日：2014-10-09

    Applicant: Atmel Corporation

    Inventor： Laurentiu Birsan ,  Frode Milch Pedersen ,  Nicolas Graffet ,  Stein Danielsen ,  Sebastien Jouin

    IPC: G06F13/28 ,  G01R31/08

    CPC classification number: G06F13/28

    Abstract: Systems and methods for direct memory access are described. One example system includes a memory module that includes a first memory portion that maintains transfer descriptors of direct memory access (DMA) channels, and a second memory portion that maintains transfer descriptors of enabled DMA channels. The system includes a controller coupled to the memory module, the controller includes one or more DMA channels coupled to a system bus, a channel arbiter that selects one of the enabled DMA channels as an active DMA channel for data transfer including re-arbitrating after each burst or beat in a given transfer, and an active channel buffer that receives a transfer descriptor of the active DMA channel from the second memory portion. The controller is configured to write back the transfer descriptor of the active DMA channel into the second memory portion when the active DMA channel loses arbitration.

    Abstract translation: 描述用于直接存储器访问的系统和方法。 一个示例系统包括存储器模块，该存储器模块包括保持直接存储器访问（DMA）通道的传送描述符的第一存储器部分和维持已使能的DMA通道的传送描述符的第二存储器部分。 该系统包括耦合到存储器模块的控制器，控制器包括耦合到系统总线的一个或多个DMA通道，通道仲裁器，其选择使能的DMA通道中的一个作为用于数据传输的活动DMA通道，包括在每一个之后重新仲裁 在给定传送中突发或跳动，以及从第二存储器部分接收活动DMA通道的传输描述符的活动通道缓冲器。 控制器被配置为当活动DMA通道失去仲裁时将有效DMA通道的传输描述符写回第二存储器部分。

    Direct memory access controller
    7.
    发明授权
    Direct memory access controller 有权
    直接内存访问控制器

    公开(公告)号：US08880756B1

    公开(公告)日：2014-11-04

    申请号：US13932925

    申请日：2013-07-01

    Applicant: Atmel Corporation

    Inventor： Laurentiu Birsan ,  Frode Milch Pedersen ,  Nicolas Graffet ,  Stein Danielsen ,  Sebastien Jouin

    IPC: G06F13/28 ,  G01R31/08

    CPC classification number: G06F13/28

    Abstract: Systems and methods for direct memory access are described. One example system includes a memory module that includes a first memory portion that maintains transfer descriptors of direct memory access (DMA) channels, and a second memory portion that maintains transfer descriptors of enabled DMA channels. The system includes a controller coupled to the memory module, the controller includes one or more DMA channels coupled to a system bus, a channel arbiter that selects one of the enabled DMA channels as an active DMA channel for data transfer including re-arbitrating after each burst or beat in a given transfer, and an active channel buffer that receives a transfer descriptor of the active DMA channel from the second memory portion. The controller is configured to write back the transfer descriptor of the active DMA channel into the second memory portion when the active DMA channel loses arbitration.

    Abstract translation: 描述用于直接存储器访问的系统和方法。 一个示例系统包括存储器模块，该存储器模块包括保持直接存储器访问（DMA）通道的传送描述符的第一存储器部分和维持已使能的DMA通道的传送描述符的第二存储器部分。 该系统包括耦合到存储器模块的控制器，控制器包括耦合到系统总线的一个或多个DMA通道，通道仲裁器，其选择使能的DMA通道中的一个作为用于数据传输的活动DMA通道，包括在每一个之后重新仲裁 在给定传送中突发或跳动，以及从第二存储器部分接收活动DMA通道的传输描述符的活动通道缓冲器。 控制器被配置为当活动DMA通道失去仲裁时将有效DMA通道的传输描述符写回第二存储器部分。

    Peripheral register parameter refreshing
    8.
    发明授权
    Peripheral register parameter refreshing 有权

    公开(公告)号：US09690726B2

    公开(公告)日：2017-06-27

    申请号：US14538305

    申请日：2014-11-11

    Applicant: Atmel Corporation

    Inventor： Laurentiu Birsan ,  Stein Danielsen

    IPC: G06F13/28 ,  H03M1/12 ,  H03M1/18

    CPC classification number: G06F13/287 ,  H03M1/12 ,  H03M1/18

    Abstract: Systems, methods, circuits and computer-readable mediums for peripheral sequencing using an access sequence are disclosed. In some implementations, a control register and status register in a peripheral are initialized with control data for selecting peripheral registers of the peripheral to be refreshed during an access sequence. For each peripheral register to be refreshed during the access sequence: a data register of the peripheral register is accessed; the peripheral register is refreshed; and the status register is updated with a current status of the access sequence. The access sequence is determined to be completed based on contents of the status register.

    Centralized peripheral access protection
    10.
    发明授权
    Centralized peripheral access protection 有权
    集中式外设访问保护

    公开(公告)号：US09552385B2

    公开(公告)日：2017-01-24

    申请号：US13965020

    申请日：2013-08-12

    Applicant: Atmel Corporation

    Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Stein Danielsen ,  Francois Fosse ,  Thierry Delalande ,  Ivar Holand ,  James Hallman

    IPC: G06F13/362 ,  G06F17/30 ,  G06F13/40 ,  G06F13/12 ,  G06F11/00

    CPC classification number: G06F9/526 ,  G06F11/00 ,  G06F11/004 ,  G06F13/122 ,  G06F13/28 ,  G06F13/362 ,  G06F13/4004 ,  G06F13/4282 ,  G06F17/30362 ,  G06F2201/825

    Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

    Abstract translation: 公开了针对被配置为保护系统中的一个或多个外围组件的中央外围设备访问控制器（PAC）的实现。 在一些实现中，PAC存储可以由软件设置或清除的数据。 该数据对应于被路由到对应的外围组件的PAC的输出信号。 当数据指示外设“未锁定”时，PAC将允许写入传输到外设组件中的寄存器。 当数据指示外设组件“锁定”时，PAC将拒绝对外设组件中的寄存器进行写入传输，并以错误结束。

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