公开(公告)号：US20110297928A1

公开(公告)日：2011-12-08

申请号：US13117588

申请日：2011-05-27

申请人： Atsuo ISOBE ,  Yoshinori IEDA ,  Keitaro IMAI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Yuki HATA

发明人： Atsuo ISOBE ,  Yoshinori IEDA ,  Keitaro IMAI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Yuki HATA

IPC分类号： H01L27/105

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

摘要： The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.

摘要翻译： 提供了一种半导体器件，其中包括第一晶体管，第二晶体管和电容器的多个存储单元被布置成矩阵，并且布线（也称为位线）用于连接其中一个存储单元和另一个 第一晶体管中的一个存储单元和源极或漏极区域通过导电层和设置在其间的第二晶体管中的源极或漏极电连接。 利用这种结构，与第一晶体管中的源极或漏极以及第二晶体管中的源极或漏极连接到不同布线的结构相比，可以减少布线的数量。 因此，可以提高半导体器件的集成度。

公开(公告)号：US20120032171A1

公开(公告)日：2012-02-09

申请号：US13193734

申请日：2011-07-29

申请人： Toshihiko SAITO ,  Yuki HATA ,  Kiyoshi KATO

发明人： Toshihiko SAITO ,  Yuki HATA ,  Kiyoshi KATO

IPC分类号： H01L27/088 ,  H01L29/786

CPC分类号： H01L27/124 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/1225 ,  H01L28/40

摘要： An object is to miniaturize a semiconductor device. Another object is to reduce the area of a driver circuit of a semiconductor device including a memory cell. The semiconductor device includes an element formation layer provided with at least a first semiconductor element, a first wiring provided over the element formation layer, an interlayer film provided over the first wiring, and a second wiring overlapping with the first wiring with the interlayer film provided therebetween. The first wiring, the interlayer film, and the second wiring are included in a second semiconductor element. The first wiring and the second wiring are wirings to which the same potentials are supplied.

摘要翻译： 目的是使半导体器件小型化。 另一个目的是减小包括存储单元的半导体器件的驱动电路的面积。 半导体器件包括至少设置有第一半导体元件的元件形成层，设置在元件形成层上的第一布线，设置在第一布线上的中间膜，和与第一布线重叠的第二布线，设置有夹层膜 之间。 第一布线，层间膜和第二布线包括在第二半导体元件中。 第一布线和第二布线是提供相同电位的布线。

公开(公告)号：US20070182442A1

公开(公告)日：2007-08-09

申请号：US11669399

申请日：2007-01-31

申请人： Yuki HATA ,  Tomoyuki IWABUCHI ,  Akihiro KIMURA ,  Shuhei NAGATSUKA

发明人： Yuki HATA ,  Tomoyuki IWABUCHI ,  Akihiro KIMURA ,  Shuhei NAGATSUKA

IPC分类号： G01R31/00

CPC分类号： G09G3/006 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2320/029

摘要： To provide a display device having a test circuit with high accuracy for testing in the step after a counter substrate is attached and before shipping, and to provide a display device having a correction circuit inside the display device, for the case where a defect occurs. A pixel circuit operated by a gate line and a source line, a first wiring formed at the same time as the gate line, a second wiring formed at the same time as the source line, and a test circuit of detecting a defect of the pixel circuit by using potentials of the first wiring and the second wiring are provided over a substrate.

摘要翻译： 为了提供具有高精度的测试电路的显示装置，用于在对置基板被安装并运送之前的步骤中进行测试，并且在发生缺陷的情况下提供具有校正电路的显示装置。 由栅极线和源极线操作的像素电路，与栅极线同时形成的第一布线，与源极线同时形成的第二布线，以及检测像素的缺陷的测试电路 通过使用第一布线和第二布线的电位的电路设置在基板上。