公开(公告)号：US20110297928A1

公开(公告)日：2011-12-08

申请号：US13117588

申请日：2011-05-27

申请人： Atsuo ISOBE ,  Yoshinori IEDA ,  Keitaro IMAI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Yuki HATA

发明人： Atsuo ISOBE ,  Yoshinori IEDA ,  Keitaro IMAI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Yuki HATA

IPC分类号： H01L27/105

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

摘要： The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.

摘要翻译： 提供了一种半导体器件，其中包括第一晶体管，第二晶体管和电容器的多个存储单元被布置成矩阵，并且布线（也称为位线）用于连接其中一个存储单元和另一个 第一晶体管中的一个存储单元和源极或漏极区域通过导电层和设置在其间的第二晶体管中的源极或漏极电连接。 利用这种结构，与第一晶体管中的源极或漏极以及第二晶体管中的源极或漏极连接到不同布线的结构相比，可以减少布线的数量。 因此，可以提高半导体器件的集成度。

公开(公告)号：US20120112191A1

公开(公告)日：2012-05-10

申请号：US13270455

申请日：2011-10-11

申请人： Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Shuhei NAGATSUKA ,  Yuto YAKUBO ,  Jun KOYAMA

发明人： Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Shuhei NAGATSUKA ,  Yuto YAKUBO ,  Jun KOYAMA

IPC分类号： H01L29/16

CPC分类号： H01L27/1156 ,  G11C11/403 ,  G11C16/0433 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1225 ,  H01L28/40

摘要： A data retention period in a semiconductor device or a semiconductor memory device is lengthened. The semiconductor device or the semiconductor memory includes a memory circuit including a first transistor including a first semiconductor layer and a first gate and a second transistor including a second semiconductor layer, a second gate, and a third gate The first semiconductor layer is formed at the same time as a layer including the second gate.

摘要翻译： 半导体器件或半导体存储器件中的数据保持期延长。 半导体器件或半导体存储器包括存储电路，该存储器电路包括第一晶体管，其包括第一半导体层和第一栅极，第二晶体管包括第二半导体层，第二栅极和第三栅极。第一半导体层形成在 与包括第二门的层相同。

公开(公告)号：US20110186949A1

公开(公告)日：2011-08-04

申请号：US13084996

申请日：2011-04-12

申请人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO ,  Takaaki KOEN ,  Yuto YAKUBO ,  Makoto YANAGISAWA ,  Hisashi OHTANI ,  Eiji SUGIYAMA ,  Nozomi HORIKOSHI

发明人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO ,  Takaaki KOEN ,  Yuto YAKUBO ,  Makoto YANAGISAWA ,  Hisashi OHTANI ,  Eiji SUGIYAMA ,  Nozomi HORIKOSHI

IPC分类号： H01L29/66

CPC分类号： G06K19/07735 ,  G06K19/07722 ,  G06K19/07794 ,  H01L23/295 ,  H01L23/3157 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 106 to 1014 Ω/cm2 is formed on at least one surface of each structure body.

摘要翻译： 一种能够进行无线通信的半导体装置，其在外力方面具有高的可靠性，特别是按压力，并且能够防止集成电路中的静电放电，而不会妨碍电波的接收。 半导体器件包括连接到集成电路的片上天线和将接收到的电波中包含的信号或功率发送到片上天线而不接触的增强天线。 在半导体器件中，集成电路和片上天线插入通过用树脂浸渍纤维体而形成的一对结构体之间。 其中一个结构体设置在片上天线和增强天线之间。 在每个结构体的至少一个表面上形成表面电阻值为大约106至1014Ω·cm 2 / cm 2的导电膜。

公开(公告)号：US20120293210A1

公开(公告)日：2012-11-22

申请号：US13471922

申请日：2012-05-15

申请人： Yuto YAKUBO ,  Shuhei NAGATSUKA

发明人： Yuto YAKUBO ,  Shuhei NAGATSUKA

IPC分类号： H03K19/0948 ,  H01L25/00

CPC分类号： G11C19/28 ,  H01L27/0688 ,  H01L27/11807 ,  H01L27/1203 ,  H01L27/1225 ,  H01L2924/0002 ,  H03K19/0948 ,  H03K19/0963 ,  H03K19/215 ,  H01L2924/00

摘要： A novel logic circuit which retains data even when power supply is stopped is provided. Further, a novel logic circuit with low power consumption is provided. In the logic circuit, a comparator comparing two output nodes, a charge retaining portion, and an output-node-potential determining portion are electrically connected to each other. Thus, the logic circuit can retain data even when power supply is stopped. In addition, the total number of transistors included in the logic circuit can be reduced. Further, a transistor including an oxide semiconductor and a transistor including silicon are stacked, whereby the area of the logic circuit can be reduced.

摘要翻译： 提供了即使在电源停止时也保持数据的新型逻辑电路。 此外，提供了一种具有低功耗的新型逻辑电路。 在逻辑电路中，比较两个输出节点的比较器，电荷保持部分和输出节点电位确定部分彼此电连接。 因此，即使电源停止，逻辑电路也可以保留数据。 此外，可以减少包括在逻辑电路中的晶体管的总数。 此外，堆叠包括氧化物半导体和包括硅的晶体管的晶体管，由此可以减小逻辑电路的面积。

公开(公告)号：US20120293207A1

公开(公告)日：2012-11-22

申请号：US13471920

申请日：2012-05-15

申请人： Yuto YAKUBO ,  Shuhei NAGATSUKA

发明人： Yuto YAKUBO ,  Shuhei NAGATSUKA

IPC分类号： H01L25/00

CPC分类号： H01L27/1225 ,  H01L27/0688 ,  H01L27/092

摘要： A novel logic circuit in which data is held even after power is turned off is provided. Further, a novel logic circuit whose power consumption can be reduced is provided. In the logic circuit, a comparator comparing two output nodes, a charge holding portion, and an output-node-potential determining portion are electrically connected to each other. Such a structure enables data to be held in the logic circuit even after power is turned off. Further, the total number of transistors in the logic circuit can be reduced. Furthermore, the area of the logic circuit can be reduced by stacking a transistor including an oxide semiconductor and a transistor including silicon.

摘要翻译： 提供即使在关闭电源之后保持数据的新型逻辑电路。 此外，提供了能够降低功耗的新颖的逻辑电路。 在逻辑电路中，比较两个输出节点，电荷保持部分和输出节点电势确定部分的比较器彼此电连接。 这样的结构即使在电源关闭之后也能够将数据保存在逻辑电路中。 此外，可以减少逻辑电路中的晶体管总数。 此外，可以通过堆叠包括氧化物半导体的晶体管和包括硅的晶体管来降低逻辑电路的面积。

公开(公告)号：US20100078787A1

公开(公告)日：2010-04-01

申请号：US12567946

申请日：2009-09-28

申请人： Yuto YAKUBO

发明人： Yuto YAKUBO

IPC分类号： H01L25/16

CPC分类号： H01L23/645 ,  G06K19/07749 ,  H01L23/60 ,  H01L23/642 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： To provide a semiconductor device whose reliability is improved by increase in resistance to external stress and electrostatic discharge with reduction in thickness and size achieved. An IC chip provided with an integrated circuit and a resonant capacitor portion, an antenna provided over the IC chip, and a conductive blocking body provided so as to at least partially overlap the antenna with an insulating film interposed therebetween are included. A capacitor is formed with a layered structure of the antenna, the insulating film over the antenna, and the conductive blocking body over the insulating film.

摘要翻译： 提供通过增加抵抗外部应力和静电放电而获得可靠性的半导体器件，其厚度和尺寸的减小。 包括设置有集成电路和谐振电容器部分的IC芯片，设置在IC芯片上的天线以及设置成至少部分地与天线重叠的导电阻挡体和插入其间的绝缘膜。 电容器形成有天线的分层结构，天线上的绝缘膜和绝缘膜上的导电阻挡体。