摘要:
To correct sudden phase changes, a device for phase correction (20) and a common control unit (10) are described, the latter switching the gain factor for the amplifier stage (30) and, at times coordinated with this, delivering phase correction values of suitable size to the device for phase correction (20), where the control unit (10) uses knowledge about fixed parameters, such as delay times and properties of sudden phase changes, when changing over the amplifier stages.
摘要:
The present invention provides an arrangement and a method for synchronizing a signal processing apparatus with a received signal which has a characteristic signal content. The arrangement has a first control loop (1, 20, 3, 4), which readjusts the signal processing apparatus with respect to the characteristic signal content on a content basis, and a second control loop (1, 21, 3, 4), which readjusts a flow control device (4) in the signal processing apparatus with respect to the times at which the characteristic signal content appears, the first control loop (1, 20, 3, 4) and the second control loop (1, 21, 3, 4) being coupled such that a unique association is achieved between the position of the characteristic signal content in the received signal and the associated appearance time.
摘要:
A comparator unit is used to compare an actual transmission time signal with a nominal transmission time signal and to produce a difference signal from the discrepancy, from which difference signal a correction signal is produced in a control unit. This correction signal is used to control a correction unit, which compresses or extends an applied input data signal, thus changing the phase angle of the output data signal so as to minimize the discrepancy between the transmission times. The discrepancy is corrected independently of the system clock, and the correction speed is set variably.
摘要:
To support a plurality of different mobile radio standards in mobile radio terminal devices using a single system oscillator, a sampling rate converter converts the sampling rates from an input rate to an output rate and additionally outputs control information which is suitable for operating signal processing components. The components receiving the control information are arranged in the signal flow upstream of the sampling rate converter, on average exactly at a virtual sampling frequency. The virtual sampling pattern is mapped onto the frame of the physical operating clock by simply gating out edges of the physical operating clock. Using the control signal, a clock control device generates a masked clock that has, on average, an edge repetition rate which corresponds to the virtual sampling frequency of the samples or to an integer multiple thereof.