摘要:
There is provided a demodulator that makes it possible to reduce or avoid deterioration in demodulation performance due to nonlinearity of input amplitude-frequency characteristics of a variable capacitive element included in an analog control signal input section of a frequency variable oscillator, while suppressing an influence of noise. The demodulator includes: a low-resolution A/D converter that performs analog-digital conversion of a first phase difference signal to generate a second phase difference signal that is digital; a low-resolution D/A converter that performs digital-analog conversion of the second phase difference signal to generate a third phase difference signal; an analog subtractor that subtracts the third phase difference signal from the first phase difference signal to generate a first control signal; an ADPLL that generates a second control signal; and an FVO that generates the oscillation signal on the basis of the first control signal and the second control signal.
摘要:
In an ultra-wideband (“UWB”) receiver, a received UWB signal is periodically digitized as a series of ternary samples. The samples are continuously correlated with a predetermined preamble sequence to develop a correlation value. When the value exceeds a predetermined threshold, indicating that the preamble sequence is being received, estimates of the channel impulse response (“CIR”) are developed. When a start-of-frame delimiter (“SFD”) is detected, the best CIR estimate is provided to a channel matched filter (“CMF”) substantially to filter channel-injected noise.
摘要:
Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase; when the data signal is oscillating at the first phase, output a first logic value; and when the data signal is oscillating at the second phase, output a second logic value, the output of the fast phase change detection circuit being used to determine whether the first output signal or the second output signal will be utilized in the feedback loop of the low bandwidth phase lock loop.
摘要:
Several circuits and methods for transferring an input data signal in a digital isolator are disclosed. In an embodiment, the digital isolator includes an isolation element, input circuit, and output circuit. The isolation element includes at least one input node and at least one output node, the input circuit is electronically coupled to the input node and generates modulated differential data signals based on modulating the input data signal on a carrier signal. The input circuit operates using a first supply voltage with respect to a first ground. The output circuit is electronically coupled to the output node to receive the modulated differential data signals, operates using a second supply voltage with respect to a second ground and includes a frequency-shift keying demodulator configured to generate a demodulated data signal in response to detection of presence of the carrier signal. The output circuit further generates an output data signal.
摘要:
Provided are a power supply device, a power receiving device, a charging system, and an obstacle detection method that obtain a sufficient obstacle detection sensitivity even when an obstacle is small. A modulation unit (202) performs amplitude modulation or phase modulation on a test data sequence output from a test data sequence storage unit (201). A power control unit (203) generates, according to an instruction from a determination unit (204), a power control signal for increasing the power level of the test data sequence every time when the test data sequence is transmitted. The determination unit (204) determines whether there is an obstacle between the power receiving device and the power supply device based on whether the test data sequence output from the test data sequence storage unit (201) coincides with the test data sequence output from a power-transmitting-side receiving circuit (124).
摘要:
Provided are a power supply device, a power receiving device, a charging system, and an obstacle detection method that obtain a sufficient obstacle detection sensitivity even when an obstacle is small. A modulation unit (202) performs amplitude modulation or phase modulation on a test data sequence output from a test data sequence storage unit (201). A power control unit (203) generates, according to an instruction from a determination unit (204), a power control signal for increasing the power level of the test data sequence every time when the test data sequence is transmitted. The determination unit (204) determines whether there is an obstacle between the power receiving device and the power supply device based on whether the test data sequence output from the test data sequence storage unit (201) coincides with the test data sequence output from a power-transmitting-side receiving circuit (124).
摘要:
A periodically resetting integration angle demodulation device and a method using the same is disclosed, which uses a waveform multiplier and a periodically resetting integrator to modulate a continuous-time angle modulation signal into a discrete-time signal. The waveform multiplier multiplies the continuous-time angle modulation signal by a square wave signal whose frequency is integer times a carrier frequency, and then transmits the continuous-time angle modulation signal to a periodically resetting integrated circuit. The periodically resetting integrated circuit performs integration during a carrier period to generate a discrete-time angle modulation output signal. The present invention can greatly reduce the difficulty for designing an optical sensing system in the front end without limiting a modulation depth. Besides, the present invention achieves a small volume, high speed, high sensitivity, high reliability, high performance and high condition-adapting properties.
摘要:
A regenerative selective logarithmic detector amplifier (LDA) can have integrated FM demodulation capabilities. It can receive a wired or wireless FM modulated signal and amplify or demodulate it with high sensitivity, high skirt ratio and minimized noise when compared to the prior art. When used in conjunction with other circuits such as a PLL or mixer, it can improve interference rejection and frequency selectivity and be locked on a precise channel in frequency and phase. The LDA produces intermittent oscillations that are self-quenched when reaching a given threshold. It also embeds the circuitry to perform direct FM discrimination. FM demodulation process is completed by a simple analog or digital frequency to voltage converter. This plus the fact that the instantaneous regeneration gain is low-medium permit to detect signals of small amplitudes buried in the noise.
摘要:
In an ultra-wideband (“UWB”) receiver, a received UWB signal is periodically digitized as a series of ternary samples. The samples are continuously correlated with a predetermined preamble sequence to develop a correlation value. When the value exceeds a predetermined threshold, indicating that the preamble sequence is being received, estimates of the channel impulse response (“CIR”) are developed. When a start-of-frame delimiter (“SFD”) is detected, the best CIR estimate is provided to a channel matched filter (“CMF”) substantially to filter channel-injected noise.
摘要:
Described herein is a wireless transceiver and related method that enables ultra low power transmission and reception of wireless communications. In an example embodiment of the wireless transceiver, the wireless transceiver receives a first-reference signal having a first-reference frequency. The wireless transceiver then uses the first-reference signal to injection lock a local oscillator, which provides a set of oscillation signals each having an oscillation frequency that is equal to the first-reference frequency, and each having equally spaced phases. Then the wireless transceiver combines the set of oscillation signals into an output signal having an output frequency that is one of (i) a multiple of the first-reference frequency (in accordance with a transmitter implementation) or (ii) a difference of (a) a second-reference frequency of a second-reference signal and (b) a multiple of the first- reference frequency (in accordance with a receiver implementation).